英伟达ASIC Physical Design Engineer

In a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be responsible for leading and defining timing signoff design methodologies of complex and world class chips/IPs. In this position, your responsibilities may include, but not be limited to: • Defining and implementing signoff methodology for all areas related to timing analysis, Circuit Quality, Extraction and noise glitch analysis； • Developing robust ASIC design and verification methodology to meet performance requirements including PVT corner definition for design convergence, clock uncertainty requirements, timing budgeting, repeater planning, automatic constraints/exceptions generation & management, and other key differentiating capabilities for quality & efficient timing closure； • Working closely with process technology team to understand process characteristics and setting appropriate design constraints to model on-chip variation effects, power-supply variation, process aging and other PV/Si miscorrelation effects in timing analysis flows； • Engaging closely with Design teams to understand the design & convergence challenges and derive methods to provide recipes with a focus on PPA & TAT optimizations； • Developing timing flows, understand design requirements/objectives and develop signoff conditions and milestone checklists appropriate with the design project goals. Work with 3rd party EDA vendors to resolve issues and drive improvements in design convergence and signoff； • Lead full chip timing signoff work, including SDC quality check, timing aware physical implementation guide, timing analysis and signoff.

In a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be responsible for leading and defining timing signoff design methodologies of complex and world class chips/IPs. In this position, your responsibilities may include, but not be limited to: • Defining and implementing signoff methodology for all areas related to timing analysis, Circuit Quality, Extraction and noise glitch analysis； • Developing robust ASIC design and verification methodology to meet performance requirements including PVT corner definition for design convergence, clock uncertainty requirements, timing budgeting, repeater planning, automatic constraints/exceptions generation & management, and other key differentiating capabilities for quality & efficient timing closure； • Working closely with process technology team to understand process characteristics and setting appropriate design constraints to model on-chip variation effects, power-supply variation, process aging and other PV/Si miscorrelation effects in timing analysis flows； • Engaging closely with Design teams to understand the design & convergence challenges and derive methods to provide recipes with a focus on PPA & TAT optimizations； • Developing timing flows, understand design requirements/objectives and develop signoff conditions and milestone checklists appropriate with the design project goals. Work with 3rd party EDA vendors to resolve issues and drive improvements in design convergence and signoff； • Lead full chip timing signoff work, including SDC quality check, timing aware physical implementation guide, timing analysis and signoff.

1. 致力打造世界一流的深度学习硬件计算平台， 跟踪深度学习及系统硬件架构的发展，设计开发高性能低功耗的架构、芯片及硬件产品。 2. 针对阿里巴巴集团业务发展需求，与阿里巴巴的算法和业务团队和作， 规划设计与业务相匹配的异构计算软硬件产品构架。 3. 确保前端设计的质量检查，以及跟后端流程的协作。 1. Build the world-class deep learning platforms. Follow closely with the latest innovations on deep learning algorithms and accelerator architecture. Architect and design deep learning HW acceleration platform for high performance and low power. 2. Target at the specific computation needs of driving business growth. Collaborate with Alibaba algorithm and business teams. Architect and develope heterogenous platforms that drive business growth. 3. Own front-end design quality checks and reviews to present the physical design team with high-quality RTL.

In a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be responsible for leading and defining timing signoff design methodologies of complex and world class chips/IPs. In this position, your responsibilities may include, but not be limited to: • Defining and implementing signoff methodology for all areas related to timing analysis, Circuit Quality, Extraction and noise glitch analysis； • Developing robust ASIC design and verification methodology to meet performance requirements including PVT corner definition for design convergence, clock uncertainty requirements, timing budgeting, repeater planning, automatic constraints/exceptions generation & management, and other key differentiating capabilities for quality & efficient timing closure； • Working closely with process technology team to understand process characteristics and setting appropriate design constraints to model on-chip variation effects, power-supply variation, process aging and other PV/Si miscorrelation effects in timing analysis flows； • Engaging closely with Design teams to understand the design & convergence challenges and derive methods to provide recipes with a focus on PPA & TAT optimizations； • Developing timing flows, understand design requirements/objectives and develop signoff conditions and milestone checklists appropriate with the design project goals. Work with 3rd party EDA vendors to resolve issues and drive improvements in design convergence and signoff； • Lead full chip timing signoff work, including SDC quality check, timing aware physical implementation guide, timing analysis and signoff.