英伟达ASIC Physical Design Engineer

任职要求

• MS in EE, CS or Microelectronics with 1+ year experience is preferred
• Project experience in IC design implementation.
• Courses taken in circuit design, digital design
• Hand-on experience in EDA software from Synopsys (FC/DC/PT/Formality), Cadence (RC…

工作职责

• STA for hierarchical design.
• Constraints creation and validation, timing budget.
• Timing closure for both partition and full chip level.
• Special timing closure, such as io, test, clock etc.
• Synthesis, Netlist quality check, Formal Verification.
• Implement chip partition and floorplan.
• Function eco creation.
• Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout).
• Flow automation development, Methodology in any of above areas.