英伟达ASIC Physical Design Engineer - New College Grad 2026

At NVIDIA, we pride ourselves in having energy efficient products. We believe that continuing to maintain our products' energy efficiency compared to the competition is key to our continued success. Our team is responsible for researching, developing, and deploying methodologies to help NVIDIA's products become more energy efficient; and is responsible for building energy models that integrate into architectural simulators, RTL simulation, and emulation platforms. Key responsibilities include developing techniques to model, analyze, and reduce the power consumption of NVIDIA GPUs. As a member of the Power Modeling, Methodology, and Analysis Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement energy modeling techniques for NVIDIA's next-generation GPUs and Tegra SOCs. Your contributions will help us gain early insight into the energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.  What you’ll be doing: • Work with architects and performance architects to develop an energy-efficient GPU. • Develop methodologies and workflows to select and run a wide variety of workloads to train models using ML and/or statistical techniques. • Develop methodologies to improve the accuracy of energy models under various constraints, such as, process, timing, floorplan and layout. • Correlate the predicted energy from models created at different stages of the design cycle, with the goal of bridging early estimates to silicon. • Develop tools to debug energy inefficiencies observed in various workloads run on silicon, RTL and architectural simulators. Work with architects to fix the identified energy inefficiencies. • Work with performance, verification and emulation methodology and infrastructure development teams to integrate energy models into their platforms. • Prototype new architectural features, create an energy model, and analyze the system impact.

• Chip integration and netlist generation • Synthesis • RTL/netlist quality check, Formal Verification, constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level; Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation; Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Flow automation development for above areas; Methodology in any of above areas.

THE ROLE: We are looking for an adaptive, self-motivative physical design engineer to join our team. As a key contributor, you will be part of a engineering team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Phyiscal Design Engineering team, as part of SoC team, furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

1. 致力打造世界一流的深度学习硬件计算平台， 跟踪深度学习及系统硬件架构的发展，设计开发高性能低功耗的架构、芯片及硬件产品。 2. 针对阿里巴巴集团业务发展需求，与阿里巴巴的算法和业务团队和作， 规划设计与业务相匹配的异构计算软硬件产品构架。 3. 确保前端设计的质量检查，以及跟后端流程的协做。 1. Build the world-class deep learning platforms. Follow closely with the latest innovations on deep learning algorithms and accelerator architecture. Architect and design deep learning HW acceleration platform for high performance and low power. 2. Target at the specific computation needs of driving business growth. Collaborate with Alibaba algorithm and business teams. Architect and develope heterogenous platforms that drive business growth. 3. Own front-end design quality checks and reviews to present the physical design team with high-quality RTL.