英伟达ASIC Physical Design Engineer
任职要求
• MS in EE, CS or Microelectronics with 1+ year experience is preferred
• Project experience in IC design implementation.
• Courses taken in circuit design, digital design
• Hand-on experience in EDA software from Synopsys (FC/DC/PT/Formality), Cadence (RC…工作职责
• STA for hierarchical design. • Constraints creation and validation, timing budget. • Timing closure for both partition and full chip level. • Special timing closure, such as io, test, clock etc. • Synthesis, Netlist quality check, Formal Verification. • Implement chip partition and floorplan. • Function eco creation. • Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout). • Flow automation development, Methodology in any of above areas.
• Chip integration and netlist generation • Synthesis • RTL/netlist quality check, Formal Verification, constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level; Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation; Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Flow automation development for above areas; Methodology in any of above areas.
• Chip integration and netlist generation • Synthesis • RTL/netlist quality check, Formal Verification, constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level; Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation; Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Flow automation development for above areas; Methodology in any of above areas.
• Chip integration and netlist generation • Synthesis, RTL/netlist quality check, Formal Verification • Constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure • Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation and method development • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Methodology and flow automation development for above areas.
• Develop and validate flows for ASIC backend library quality check, maintain and release methodology. • Build and validate flows for design level lib cells usage auditing. • Setup flows/methodology on library in deep submicron physical effects such as aging, self heating, etc.