AMDSOC DFT DV Engineer
任职要求
Familiar with Linux Environment (including shell scripting and linux gnu tools) Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.) Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification Should have excellent communication skills (both written and oral) Strong problem solving skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Shanghai #LI-VC1
工作职责
THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the SOC level Build testbench components to support the next generation products Maintain or improve current test libraries to support SOC level testing Maintain and improve current hardware simulation environment to speed up the runtime performance and improve the debug facility Verify block/chip level DFX design and features. Develop high coverage and cost effective test patterns. Provide support on Post silicon bring up Provide technical support to other teams
THE ROLE: The S3 DFT team fully own AMD S3BU (Strategic Silicon Solution Business Unit) SOC DFT definition, Implementation, verification till final silicon bring up. We design the APUs mainly for consoles. Design Verification team is part of the whole chip design team and responsible to make sure the RTL quality. You will be working with DFT design and front-end team to verify the debug logic and make sure it is working on post-Si. THE PERSON: Has related knowledge for design verification and good debug skills. Familiar with entire ASIC design flow Has good communication skills and be able to work both independently and in a team. Should have strong problem-solving skills KEY RESPONSIBILITIES: Qualified candidate will perform some or all functions below: Develop test plan according to the specification and review with Architect and Designer. Develop test scenarios to verify the design and analyze the coverage. Complete the verification task before TO. Participate in ATE bring-up and debug the DFT patterns on ATE.
1、根据芯片总体设计要求进行IP模块前端设计，SOC Integration； 2、根据模块规格要求，与软件确定软硬件划分，完成数字电路模块 （包括DFT）RTL设计，包括电路综合、时序检查 （Timing check）、功能验证，Formal Verification， 仿真等； 3、成模块级功耗，面积，性能分析； 4、给后端设计提供必要的支持，在后端设计完成后进行后仿 （Post Layout Simulation）； 5、参与芯片测试和调试。
1、根据芯片总体设计要求进行IP模块前端设计，SOC Integration； 2、根据模块规格要求，与软件确定软硬件划分，完成数字电路模块（包括DFT）RTL设计，包括电路综合、时序检查（Timing Check）、功能验证，Formal Verification，仿真等； 3、成模块级功耗，面积，性能分析； 4、给后端设计提供必要的支持；在后端设计完成后进行后仿（Post Layout Simulation）； 5、参与芯片测试和调试。
1、根据芯片总体设计要求进行IP模块前端设计，SOC Integration； 2、根据模块规格要求，与软件确定软硬件划分，完成数字电路模块 （包括DFT）RTL设计，包括电路综合、时序检查 （Timing Check）、功能验证、Formal Verification， 仿真等； 3、成模块级功耗，面积，性能分析； 4、给后端设计提供必要的支持。在后端设计完成后进行后仿 （Post Layout Simulation）； 5、参与芯片测试和调试。