AMDSilicon Back-End Design Engineer
任职要求
Has knowledge with digital-circuit’s physical design implementation flow and has a strong desire to automate flow. Has good communication skills and be able to work both independently and in …
工作职责
THE ROLE: AMD CAD team is part of Design Methodology team and be responsible to deliver differentiated ASIC implementation flows (from RTL to GDSII) for all AMD products. You'll be working with the global CAD team on physical design implementation flows (from netlist to GDSII) and focus on PPA push related areas.
• As a key MMPLEX Video Design team member, you will document, implement, and deliver fully verified, high-performance, low-area, and power-efficient designs to achieve the design targets and specifications. • Participate in video-related design and analyze architectural trade-offs based on features, performance requirements, and system limitations. • Craft micro-architecture, implement in HLS/RTL, and deliver a fully verified, synthesis/timing clean design. • Collaborate and coordinate with architects, other designers, pre- and post-silicon verification, SOCD, emulation, back-end, and bringup teams to accomplish your tasks.
• As a key MMPLEX Video Design team member, you will document, implement, and deliver fully verified, high-performance, low-area, and power-efficient designs to achieve the design targets and specifications. • Participate in video-related design and analyze architectural trade-offs based on features, performance requirements, and system limitations. • Craft micro-architecture, implement in HLS/RTL, and deliver a fully verified, synthesis/timing clean design. • Collaborate and coordinate with architects, other designers, pre- and post-silicon verification, SOCD, emulation, back-end, and bringup teams to accomplish your tasks.
• As a key MMPLEX Video Design team member, you will document, implement, and deliver fully verified, high-performance, low-area, and power-efficient designs to achieve the design targets and specifications. • Participate in video-related design and analyze architectural trade-offs based on features, performance requirements, and system limitations. • Craft micro-architecture, implement in HLS/RTL, and deliver a fully verified, synthesis/timing clean design. • Collaborate and coordinate with architects, other designers, pre- and post-silicon verification, SOCD, emulation, back-end, and bringup teams to accomplish your tasks.
THE ROLE: As one of IP design team members, own for IP level design work, including architecture define (partly own or join), spec documentation, RTL coding, RTL delivery and signoff The target IP is used for all AMD mainstream products, product generation upgrade, reusability and scalibility need to be considered in architecture define and RTL maintain, as well as compliant to system application and sw/fw/hw cooperation. Need to co-work with other teams closely, include communication with AMD global soc architect and IP architect, closely work with verification team, trace and support backend work, silicon validation support. The IP team will have flexible work assignment, respect to indificual interest and the team target to achieve win-win, encourage and help individuals to discuss with global senior architectures and engineers for variants of topics and work together to resolve problems, aimed to improve both the team and individuals’ IP design capability and competivity.