长江存储Product and Test engineer(J13517)
任职要求
1) BS or MS in Electrical/Computer Engineering. 2) Experience with scripting (python/perl), C/C++. 3) Highly organized and self-motivated, good team work and communication skills. 4) The ability to work with other engineers across multiple disciplines, as well as custom…
工作职责
Wafer Sort Testing Engineer is in charge of wafer level memory product developments, including wafer level validation & production testing flow definition, test method definition and implementation, wafer level memory device characterization, qualification and customer return material analysis. Deliver qualified product to mass production as well as sustaining product for wafer level yield improvement, TTR and DPPM reduction. 2. Job Responsibilities 1) Owner of wafer level validation & production testing, characterization, qualification and customer return material analysis. 2) Define wafer level characterization, qualification and mass production test methodologies. 3) Be responsible of wafer level memory product test program development and validation on varies test platforms. Ensure delivery of test program in time. 4) Be responsible for wafer level test failure analysis and investigation of customer device/application issue during product development phase. 5) Identify device failure mechanism through electrical failure analysis, and support physical failure analysis during development and product development phase. 6) Support testing platform development with HW design engineers. 7) Support wafer level mass production yield improvement, TTR and DPPM reduction. 8) Support other teams, such as design team, PIE, RE required DOEs.
Wafer Sort Testing Engineer is in charge of wafer level memory product developments, including wafer level validation & production testing flow definition, test method definition and implementation, wafer level memory device characterization, qualification and customer return material analysis. Deliver qualified product to mass production as well as sustaining product for wafer level yield improvement, TTR and DPPM reduction. 2. Job Responsibilities 1) Owner of wafer level validation & production testing, characterization, qualification and customer return material analysis. 2) Define wafer level characterization, qualification and mass production test methodologies. 3) Be responsible of wafer level memory product test program development and validation on varies test platforms. Ensure delivery of test program in time. 4) Be responsible for wafer level test failure analysis and investigation of customer device/application issue during product development phase. 5) Identify device failure mechanism through electrical failure analysis, and support physical failure analysis during development and product development phase. 6) Support testing platform development with HW design engineers. 7) Support wafer level mass production yield improvement, TTR and DPPM reduction. 8) Support other teams, such as design team, PIE, RE required DOEs.
Develop new test equipment and procedures for camera module validation and production test. Lead Apple vendor and X-functional teams to resolve critical electrical, signal and power integrity issues Lead implementation for camera sub-system with challenging component and system requirements. Develop electronic testing prototypes for new camera features and product concepts Optics / images processing and testing knowledge would be a plus.
Develop new test equipment and procedures for camera module validation and production test. Lead Apple vendor and X-functional teams to resolve critical electrical, signal and power integrity issues Lead implementation for camera sub-system with challenging component and system requirements. Develop electronic testing prototypes for new camera features and product concepts Optics / images processing and testing knowledge would be a plus.
• Designs, develops, and implements cost-effective methods of testing and troubleshooting systems and equipment for board level product development and manufacturing. • Develop with MP test solution and test DIAGs development. Coordinate with CM guys on test requirements’ implementation. • Establish a robust MFG test solution framework for ICT and FCT from HW and SW perspectives. • Test jigs or test fixtures development and deployment. • Together with other teams, you will develop and deploy DFX methodologies for our next generation products which will serve for MFG purposes.