
长江存储模拟设计工程师(J13712)
社招全职地点:上海状态:招聘
任职要求
任职资格 Requirements: 1. Master with5+ years’ experience 2. Solid knowledge and experience on analog/mixed signal design, semiconductor process 3. Familiar with EDA tools such as Virtuoso,hspice, finesim etc 4. Experience for memory design is a plus,Experience for LDO, Regulator, Charge pump design is a plus. 5. Good team player 6. Good presentation skill 7. Self-motivated 8. Good communication skill in both written and oral English
工作职责
核心职责 As senior Design engineer in YMTC Shanghai Design Team, you will be responsible to design the analog/Mixed signal circuitry with the state of art 3D NAND Flash Memory technology. You will work with different function groups not only inside design department but also product engineering, process integration, marketing to deliver the memory products. Responsibilities: 1. In charge of multi-voltage domain power supply system for NAND VLSI SOC 2. Responsible for high voltage system design for 3D NAND Memory, including positive and negative pump design 3. Power Supply for high speed IO include LDO and DC-DC converter 4. Power Grid for state of art 3D NAND VLSI design 5. Reference system design for 3D NAND VLSI including bandgap, Power loss detector and power loss management 6. Guide Layout Engineer for floorplan and layout performance improvement/ die size optimization 7. Conducts evaluation of design results by laboratory measurement of ICs 8. Reliability analysis and design solution for 3D NAND reliability issue 9. SPEC definition of the analog circuitry to meet the product requirement 10. Design for testing circuitry 11. Support product engineer for silicon test and debug
包括英文材料
相关职位
校招平头哥秋季202
1、设计模拟 IP 的子模块 Ex. DDR5, HBM3, 芯片互连 IP, PCIe5/6 等 IP 的子模块电路; 2、PLL, DLL, CDR, CTLE, DFE 等电路设计; 3、设计电源管理相关 IP. Ex. DC2DC (Buck 更佳), LDO, 电源起始电路等; 4、设计模数转换电路(ADC) 给不同的应用场景. Ex. 电压感测器,温度感测器等; 5、根据项目需求设计 BGR, 运算放大器等,相关的模拟电路。
更新于 2025-08-04
社招3年以上A85984
1、配合电路设计工程师完成相应BLOCK的版图工作; 2、可以独立完成相应版图的DRC/LVS/ERC的验证工作; 3、优化版图并减少寄生,优化EMIR; 4、与电路设计工程师充分沟通,确保版图符合设计者的要求。
更新于 2025-03-10
社招3年以上A66857
1、配合电路设计工程师完成相应BLOCK的版图工作; 2、可以独立完成相应版图的DRC/LVS/ERC的验证工作; 3、优化版图并减少寄生,优化EMIR; 4、与电路设计工程师充分沟通,确保版图符合设计者的要求。
更新于 2023-12-21