长鑫存储工艺整合研发专家-TD Process Integration Expert(J18511)
任职要求
1.硕士及以上学历，工学、物理、机械、材料科学、微电子等理工科专业背景；
2.10年以上工艺整合经验，深入理解集成电路制造全流程，特别是与DRAM制造高度相关的关键模块工艺：光刻、刻蚀、薄膜沉积（CVD, PVD, ALD）、扩散/离子注入、化学机械平坦化、清洗等，深刻理解各工艺步骤之间的相互作用和整合挑战；
3.精通D…工作职责
1.带领团队进行工艺制程研发工作, 确定开发方向； 2.组织协调跨部门合作，和产品设计、器件、工艺部门共同合作，建立切实可行的良率提高、性能改善路线图； 3.新工艺导入，从制程整合的角度领导整个从无到有的研发工作。
1.带领团队进行工艺制程研发工作, 确定开发方向； 2.组织协调跨部门合作，和产品设计、器件、工艺部门共同合作，建立切实可行的良率提高、性能改善路线图； 3.新工艺导入，从制程整合的角度领导整个从无到有的研发工作。
1.带领团队进行工艺制程研发工作, 确定开发方向； 2.组织协调跨部门合作，和产品设计、器件、工艺部门共同合作，建立切实可行的良率提高、性能改善路线图； 3.新工艺导入，从制程整合的角度领导整个从无到有的研发工作。
1. 教育背景与专业知识：本科及以上学历，电子类、光学类、集成电路类等理工科背景优先； 2. 专业技能与资格：能使用光刻相关设备与量测工具完成工艺参数调整与实验验证，能独立分析工艺数据并输出技术报告； 3. 行业与专业经验：具有2年以上半导体光刻工艺工作经验，有光刻工艺研发经验者优先； 4. 项目/任务成果：参与过至少一项光刻工艺开发或优化项目，并形成可验证的工艺方案； 5. 其他要求：具有清晰的逻辑分析与主动推进意识，能在多部门协同中主动沟通并推动技术问题闭环。
1.Be responsible for the design and development of the device architecture of 3D NAND Flash, and deeply participate in the whole process from concept design to mass production. Utilize professional knowledge to carry out innovation at the architecture level, optimize the structure of memory cells, and improve storage density, performance and reliability. 2.Collaborate with the circuit design team to complete the efficient transformation from device physical characteristics to circuit logic, ensuring the compatibility and performance of the overall system. And increase the read and write speed and reduce power consumption. 3.Lead the research and application of new technologies, explore cutting-edge fields such as new materials and manufacturing processes, and provide technical support for the performance breakthrough of 3D NAND Flash. Through the research on industry trends, promote technological innovation and enhance product competitiveness. 4.Conduct in-depth analysis of the problems in the R&D process by using the knowledge of device physics and semiconductor processes, and put forward effective solutions. Use data analysis and modeling techniques to optimize device performance and ensure that products meet high-quality standards. 5.Lead/Participate in test chip tapeout for new memory technology development and product chip tapeout for production introduction 6.Interact with process module, material, simulation, device characterization and reliability group to optimize process flow, improve memory cell device performance and develop innovative solution to meet product requirement and qualification criteria 7. Drive cross-functional team including process module, device, product engineering, design, YE, YAE, TO, and Test to address process/technology gap and yield/margin issues