平头哥平头哥-AI 芯片PCIE 设计专家-上海
任职要求
· Minimum of 5 years of experience on PCIE design for proven silicon. · Familiar with PCIE protocol, including physical layer/data link laye…
工作职责
In this role, you will work with software and hardware engineering groups to define the cutting edge of next-generation AI SOC chips for high-performance computing platform in Data Center. · According to SOC architecture, evaluate PCIE subsystem feature requirement include but not limited to PCIE protocol/PPA improvement/SRIOV virtualization etc. · As the PCIE subsystem IP owner, integration and glue logic RTL development for various of complex SOCs, high quality IP deliver with clean Lint/cdc/rdc and timing closure. · Strong problem solving and solution for PCIE design and IP integration, work together with DV owner and Emulation to cover PCIE related features. · Participate in post silicon bring up and PCIE related issue debug.
1. 参与高速接口系统(PCIe/UCIe/Ethernet等)需求分析及Spec定义 2. 负责高速接口系统微架构定义及设计方案，并完成RTL交付，完成Lint/CDC等质量检查 3. 负责高速接口系统PPA及时序分析和优化 4. 配合上下游完成芯片验证、后端迭代、底软调试、回片测试等工作
In this role, you will work with software and hardware engineering groups to define the cutting edge of next-generation AI SOC chips for high-performance computing platform in Data Center. * as a design engineer, strong coding skill of system Verilog or Verilog to implement RTL design, develop SOC domain system/interface IP for various SOCs * familiar with ASIC flow to create complex SOCs with advanced methodologies more efficient, participated 3rd party IP integration * strong problem solving and solution for SOC design and IP integration, timing closure, silicon bring up and issue debug * Documents the high-level architecture specification that defines the chip with various sub-systems for the cutting-edge cloud applications. * Works closely with PD, power, system, and verification team to bring up the subsystem
1. 参与SoC系统需求及Spec定义与分析 2. 负责SoC top或Subsystem微架构定义及集成方案，完成RTL代码交付，完成Lint/CDC等质量检查 3. 参与SoC或Subsystem的PPA及时序分析和优化 4. 配合上下游完成芯片验证、后端迭代、底软调试、回片测试等工作
1. 负责高速接口系统(PCIE/UCIe/Ethernet等)的验证环境搭建，规划验证策略&验证方法 2. 编写和调试功能用例、性能用例、功耗用例，参与SoC Gate-level后仿真，完成验证覆盖率收集和分析 3. 配合上下游完成芯片EMU、FPGA验证、底软调试及回片测试工作