英伟达Senior Design Verification Engineer - Hardware
任职要求
• MS in electrical / computer engineering or equivalent experience. • 5+ years (MS) working experience. • Familiar with advance verification methodology, tools and flow • Fully experienced verification flow, including testplan, test, coverage model, testbench, BFM modeling. • Deep understanding in Verilog and HVL (High-level Verification Language) Ways to stand out from the crowd: • Strong programming skills in Python and C/C++is plus • Having good arch/design experience is big plus. • At least good at one of the script programing language: Perl, Shell, Ruby, Python. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We …
工作职责
• You will participate in the research of verification methodology to improve automation and productivity to produce Nvidia’s new high-quality products. • Read IAS and design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers. • You responses to build block/IP testbench based on UVM methodology. • The responsibilities include building test run and regression flow. Triage failures in regression and help designer root cause the bug. • Work includes Build various metrics (passing rate, functional coverage, etc) and monitor its health. • Take SOC verification on fullchip test environment for IPs • Analyse functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score. • Deploy the advanced verification methodology and infrastructure of the SOC/IP
• You will participate in the research of verification methodology to improve automation and productivity to produce NVIDIA's new high-quality products. • Read IAS and design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers. • You responses to build block/IP testbench based on UVM methodology. • The responsibilities include building test run and regression flow. Triage failures in regression and help designer root cause the bug. • Work includes Build various metrics (passing rate, functional coverage, etc) and monitor its health. • Take SOC verification on fullchip test environment for IPs • Analyse functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score. • Deploy the advanced verification methodology and infrastructure of the SOC/IP
• Participate in the research of verification methodology to improve automation and productivity to produce NVIDIA's new high-quality products. • Read the IAS and design specs to understand the design requirements and build a corresponding test plan. Review the testplan with arch/design engineers. • You responses to build a block/IP testbench based on UVM methodology. • The responsibilities include building a test run and a regression flow. Triage failures in regression and help the designer root cause the bug. • Work includes building various metrics (passing rate, functional coverage, etc) and monitoring its health. • Take SOC verification on full chip test environment for IPs • Analyse functional/code coverage results and identify the coverage holes. Work with the design engineer to improve the coverage score. • Deploy the advanced verification methodology and infrastructure of the SOC/IP
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages