英伟达Senior Design Verification Engineer
任职要求
• BS / MS in electrical / computer engineering or equivalent experience. • 3+ years (MS) or 5+ years (BS) working experience. • Familiar with advanced verification methodology, tools and flow • Fully experienced verification flow, including testplan, test, coverage model, testbench, and BFM modeling. • Deep understanding of Verilog and HVL (High-level Verification Language) Ways to stand out from the crowd: • Strong programming skills in Perl and C/C++is plus • Having good architectural or design experience is a big plus. • At least good at one of the scripting programming languages: Perl, Shell, Ruby, Python. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most d…
工作职责
• Participate in the research of verification methodology to improve automation and productivity to produce NVIDIA's new high-quality products. • Read the IAS and design specs to understand the design requirements and build a corresponding test plan. Review the testplan with arch/design engineers. • You responses to build a block/IP testbench based on UVM methodology. • The responsibilities include building a test run and a regression flow. Triage failures in regression and help the designer root cause the bug. • Work includes building various metrics (passing rate, functional coverage, etc) and monitoring its health. • Take SOC verification on full chip test environment for IPs • Analyse functional/code coverage results and identify the coverage holes. Work with the design engineer to improve the coverage score. • Deploy the advanced verification methodology and infrastructure of the SOC/IP
• You will participate in the research of verification methodology to improve automation and productivity to produce NVIDIA's new high-quality products. • Read IAS and design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers. • You responses to build block/IP testbench based on UVM methodology. • The responsibilities include building test run and regression flow. Triage failures in regression and help designer root cause the bug. • Work includes Build various metrics (passing rate, functional coverage, etc) and monitor its health. • Take SOC verification on fullchip test environment for IPs • Analyse functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score. • Deploy the advanced verification methodology and infrastructure of the SOC/IP
NVIDIA SOC System-ASIC team is hiring a verification engineer. In this role, you will work closely with Arch, design and verification engineers to thoroughly verify some top-level related control units (like: Fuse/Floorsweep, Strap, Reset, Sysctrl) and some silicon measurement related units from unit-level to fullchip-level. Those units are important IPs used in both NVIDIA GPU and Tegra products. What you’ll be doing: • Micro-architecture definition for System-level modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl, etc...) • Unit-level and System-level verification for System-level modules. • Own some NVIDIA internal checks to guarantee the design quality.
• Responsible for ASIC design verification for various IPs at IP and SOC levels • Responsible for reference model development and integration • Participate in IP/SOC architecture, micro-architecture reviews, interface with Architecture, SW/FW, Design, and Modeling to work out comprehensive first-time right verification plans • Contribute to the innovative verification methodology development, functional and code coverage closure. • Work on the complex TB creation, direct/random tests and drive the function and coverage to closure. • Contribute to the development of silicon and platform verification strategy and methodology • Triage the fail on SOC level with SOCV/EMU/SW team • Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection, and IP licensing
NVIDIA SOC System-ASIC team is hiring a verification engineer. In this role, you will work closely with Arch, design and verification engineers to thoroughly verify some top-level related control units (like: Fuse/Floorsweep, Strap, Reset, Sysctrl) and some silicon measurement related units from unit-level to fullchip-level. Those units are important IPs used in both NVIDIA GPU and Tegra products. What you’ll be doing: • Micro-architecture definition for System-level modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl, etc...) • Unit-level and System-level verification for System-level modules. • Own some NVIDIA internal checks to guarantee the design quality.