英伟达Silicon System Level Test Development Engineer
任职要求
• MS with 5+ years or equivalent experience in Electrical Engineering (EE), Computer Engineering (CE), Computer Science (CS), Systems Engineering, or a related field
• Rich experience at manufacturing and production test of chips, boards and systems.
• Background in creating new system tests or test conditions and good skills in Linux, Python, and Perl.
• Experience working with GPU/CPU system features and crafting test strategies.
• Deep understanding of product binning methods, optimization techniques, methods, trade-off analysis and tools for data analysis and statistics.
• Excellent problem solving, collaborative and interpersonal skills
Ways to stand out from the crowd:
• Experience in rack-level test development
• Experience in Post-Silicon validation, SW…工作职责
• Based on understanding a product feature, determine the best manufacturing stage for testing GPU/CPU hardware features. This could be ATE, socketed or board-level system test, rack-level test, or pod/cluster-level test, as needed. • Create new tests or test conditions based on an understanding of hardware features or learnings from customer returns or gaps in internal manufacturing stages. • Perform or automate test runs, analyze and visualize data to ensure a high-quality test, and guide debug for yield or escape issues. • Partner with test engineering and operations teams to implementing efficient manufacturable test solutions
-在芯片设计阶段，从系统应用和调试角度参与芯片定义 -结合业界标准规范和实际应用场景制定全面详细的validation plan -在post silicon阶段，负责芯片的bring-up和validation，分析并解决在此过程中发现的问题 -开发validation和debug所需的测试工具和脚本 -与软硬件团队合作，基于主流AI模型，进行系统性能和功耗以及稳定性的分析与优化 -在芯片量产落地阶段，负责分析并解决生产侧、服务器适配侧以及客户侧遇到的硬件和系统级问题
1、负责芯片底层软件开发和SoCBring-up; 2、负责SoC芯片的软件验证，包括Pre-silicon和Post-silicon阶段的验证； 3、负责BootRom/SoC底软开发&交付工作（MSCP/Tiano/UBoot/Coreboot/LinuxBoot/TF-A/TF-M/OpenSBI）； 4、负责Core/NOC/UCIe/PCIe/DDR/PMU/RAS等某一IP的Firmware/Driver开发； 5、负责SoC HSM/Secure Boot/TF-A/TEE OS等软件开发；负责SoC Cypto engine/安全Driver等功能开发和验证； 6、负责NIC、DPU及RDMA硬件驱动开发、特性使能以及业务场景落地。
1. 配合算法部门进行定点化及资源、架构优化，对交付的4/5G通信IP的定点化算法进行芯片架构设计及后续RTL设计和IP交付 2. 确保前端交付的各项质量检查 3. 和验证等团队协作，完成功能及时序验证 4. 和中后端团队协作，完成通信IP的物理实现及交付 5. 与其他团队合作，完成功耗、面积、性能的评估。 6. 支持软件等相关团队完成FPGA&post silicon的测试及量产工作。
一、 岗位职责 1. 负责数字芯片系统设计。 2. 负责数字芯片IP设计。 3. 和其他团队协作，完成功能验证/时序实现 以及 post silicon的测试工作。 4. 与其他团队合作，完成功耗、面积、性能的评估。 5. 确保前端交付的各项质量检查。