AMDPost-Silicon System Debug Engineer

1.Design/verify/optimize high speed IO circuit blocks used in memory products,DDR4,DDR5,LPDDR4,LPDDR5,GDDR5,GDDR6 etc.; 2.Developing advanced(sub-10ps) SerDes—advance PHY architectures, with emphasis on high-speed receivers and signal-conditioning/equalization techniques; 3.Modeling and simulations of advance analog systems,algorithm development,as well as mixed-signal system integration,bring-up and debug; 4.Work with design team,Plan/implement/verifythew hole analog circuit system; 5.Design the circuity used for test,main focus on analog block but not limited; 6.Guide layout designer floorplan/implement the layout and response post layout simulation; 7.Provide support to Product Engineering for silicon test/debug； 8.Pre-research the advanced high speed IO technology used in the next generation of DRAM.

The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Verification engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the frontend design team to understand the clocking requirements for the chip. We also understand the physical restrictions being placed on the clocks by the backend teams. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.   What you’ll be doing:  • Develop test plans, tests and verification infrastructure for verifying high-speed Clocking logic, including many aspects: function, DFT, circuit, power, physical design constraints, and etc. You would need to comprehend the functional, test and timing modes for clocks RTL and verify the modes before RTL delivery.  • You will collaborate with other verification engineers and provide creative solutions to reuse programming sequences across various verification hierarchies.  • Build verification environment using SV/UVM methodology Build reusable bus functional models, monitors, checkers and scoreboards  • Drive coverage driven verification closure  • Work with architects, designers and post-silicon teams.  • Methodology development for above tasks.

• Based on understanding a product feature, determine the best manufacturing stage for testing GPU/CPU hardware features. This could be ATE, socketed or board-level system test, rack-level test, or pod/cluster-level test, as needed. • Create new tests or test conditions based on an understanding of hardware features or learnings from customer returns or gaps in internal manufacturing stages. • Perform or automate test runs, analyze and visualize data to ensure a high-quality test, and guide debug for yield or escape issues. • Partner with test engineering and operations teams to implementing efficient manufacturable test solutions

THE ROLE: AMD Graphics Platform validation team is part of Graphics systems and customer engineering, and is responsible for validating platforms for AMD client products and graphic Products. You will be working with cross function teams globally to validate client and graphics platforms, triage/debug issues, and drive validation’s deliverables to hit platform validation milestones. THE PERSON: Bachelor +, Minimum of 6+ year hands-on industry experience in PC, laptop , Graphics , mother boards, server product test and issue debug. Excellent communication skills including English ability in oral and written Be able to work both independently and in a team. Leading technical discussion with multiple function teams and drive issue’s triage and debug. KEY RESPONSIBILITIES: Engaged in AMD Client and dGPU’s post-silicon phases , Driving to review internal & customer’s design, develop validation strategies and test plan for AMD reference or customer platform designs Create test procedures and generate technical documents as needed. Execute Post-Si Integration validation ; Track/Report validation status . Triage/debug system level issue with cross function engineering teams (Firmware , SW , diag , board design) , and root cause the issue Support new product bring-up and debug issues