英伟达Senior Chip Design and Formal Verification Engineer
任职要求
• BSc in Electrical/Computer Engineering (or MSc in Mathematics/Computer Science) • 5+ years of experience in chip design - FV, RTL design, DV, or a mix. • Strong analytical thinking and logical problem-solving skills • Experience debugging complex design issues at the RTL or functional level • Good communication skills; able to work across design and verification teams Ways to stand out from the crowd: • Exposure to formal verification concepts or tools …
工作职责
• Use your Design/Verification experience to define, model, and prove key design behaviors using formal methods. • Work closely with design, verification, and architecture teams to find bugs early and improve design quality. • Build expertise in advanced formal tools, properties, abstractions, and debug methods with mentorship from an experienced FV team. • Take part in the AI revolution, working on cutting-edge silicon architectures.
• Understand the Switch architecture and data flows • Refine the full Chip working flow to improve the entire team's efficiency & smooth the project exeuction • Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW to meet project milestones.
• Understand the Switch architecture and data flows • Refine the full Chip working flow to improve the entire team's efficiency & smooth the project exeuction • Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW to meet project milestones.
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages