英伟达Senior ASIC Design Methodology Engineer
任职要求
• Master's degree with 5+ years or equivalent experience, with IC front-end design, verification experience or flow development. • Convenience with working in Linux environment. • Solid scripting skill in Perl or Python, Makefile is a plus • Strong communication skills and demonstrated capability of working with people from different disciplines.
工作职责
• Develope in-house tools to accelerate the efficiency of ASIC front-end design and verification workflow. • Promote those in-house tools to the user group with support, and implement new features as well as fix bugs from user request • Setup automation flow to reduce the repeated manual effort for working efficiency
The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Verification engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the frontend design team to understand the clocking requirements for the chip. We also understand the physical restrictions being placed on the clocks by the backend teams. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you’ll be doing: • Develop test plans, tests and verification infrastructure for verifying high-speed Clocking logic, including many aspects: function, DFT, circuit, power, physical design constraints, and etc. You would need to comprehend the functional, test and timing modes for clocks RTL and verify the modes before RTL delivery. • You will collaborate with other verification engineers and provide creative solutions to reuse programming sequences across various verification hierarchies. • Build verification environment using SV/UVM methodology Build reusable bus functional models, monitors, checkers and scoreboards • Drive coverage driven verification closure • Work with architects, designers and post-silicon teams. • Methodology development for above tasks.
• Develop and maintain the methodology for IP development • Develop and maintain the flow automation to improve the engineering efficiency • Find and fix flow issues and help IP team to adopt