英伟达GPU Power Analysis Engineer - New College Grad 2026
任职要求
• EE, MS or PhD in related fields, or equivalent experience. • Basic understanding of concepts of energy consumption, estimation, and low power design. • Familiarity with Verilog and ASIC design principles, including knowledge of logic cells. • Good verbal/written English and interpersonal skills; much collaboration with design teams is expected. • Strong coding skills, preferably in Python, C++. • Ability to formulate and analyze algorithms, and comment o…
工作职责
• Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency. • Develop and share best practices for performing pre-silicon power analysis, Enhance internal power tools and automate best practices • Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny. • Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes. • Select and run a wide variety of workloads for power analysis, Collaborate with performance and architecture teams to validate performance of the workloads • Prototype a new architectural feature in Verilog and analyze power.
At NVIDIA, we pride ourselves in having energy efficient products. We believe that continuing to maintain our products' energy efficiency compared to the competition is key to our continued success. Our team is responsible for researching, developing, and deploying methodologies to help NVIDIA's products become more energy efficient; and is responsible for building energy models that integrate into architectural simulators, RTL simulation, and emulation platforms. Key responsibilities include developing techniques to model, analyze, and reduce the power consumption of NVIDIA GPUs. As a member of the Power Modeling, Methodology, and Analysis Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement energy modeling techniques for NVIDIA's next-generation GPUs and Tegra SOCs. Your contributions will help us gain early insight into the energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements. What you’ll be doing: • Work with architects and performance architects to develop an energy-efficient GPU. • Develop methodologies and workflows to select and run a wide variety of workloads to train models using ML and/or statistical techniques. • Develop methodologies to improve the accuracy of energy models under various constraints, such as, process, timing, floorplan and layout. • Correlate the predicted energy from models created at different stages of the design cycle, with the goal of bridging early estimates to silicon. • Develop tools to debug energy inefficiencies observed in various workloads run on silicon, RTL and architectural simulators. Work with architects to fix the identified energy inefficiencies. • Work with performance, verification and emulation methodology and infrastructure development teams to integrate energy models into their platforms. • Prototype new architectural features, create an energy model, and analyze the system impact.
At NVIDIA, we pride ourselves in having energy efficient products. We believe that continuing to maintain our products' energy efficiency compared to the competition is key to our continued success. Our team is responsible for researching, developing, and deploying methodologies to help NVIDIA's products become more energy efficient; and is responsible for building energy models that integrate into architectural simulators, RTL simulation, and emulation platforms. Key responsibilities include developing techniques to model, analyze, and reduce the power consumption of NVIDIA GPUs. As a member of the Power Modeling, Methodology, and Analysis Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement energy modeling techniques for NVIDIA's next-generation GPUs and Tegra SOCs. Your contributions will help us gain early insight into the energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements. What you’ll be doing: • Work with architects and performance architects to develop an energy-efficient GPU. • Develop methodologies and workflows to select and run a wide variety of workloads to train models using ML and/or statistical techniques. • Develop methodologies to improve the accuracy of energy models under various constraints, such as, process, timing, floorplan and layout. • Correlate the predicted energy from models created at different stages of the design cycle, with the goal of bridging early estimates to silicon. • Develop tools to debug energy inefficiencies observed in various workloads run on silicon, RTL and architectural simulators. Work with architects to fix the identified energy inefficiencies. • Work with performance, verification and emulation methodology and infrastructure development teams to integrate energy models into their platforms. • Prototype new architectural features, create an energy model, and analyze the system impact.
• Build internal profiling/analysis tools for real world application perf/power analysis at system from small to large scale. • Build infrastructure or services for data visualization/mining and management. • Work with our users to build their perf/power models on top of our tools for next generation HW design.
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 30 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. We are now looking for Physical Design Engineer in Shanghai & Beijing office. What you’ll be doing: • Analysis on placement, routing, timing, clock, power, noise and DFM and provide optimization strategy • Work on full chip clock distribution • Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention. • Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.