英伟达Physical Design, VLSI - New College Grad 2026
任职要求
• MSEE in CS/EE/ME
• Basic knowledge of VLSI digital design backend work flow
• Basic device model, processing technology, timing, noise and power in chip design
Ways to stand out from the crowd:
• Hands-on experiences in EDA software from Synopsys (DC/ICC2/STAR-RC/PT/ICV), Cadence (Genus/Innovus/Quantus/Tempus/PVS), ANSYS (Seahawk/Redhawk) etc is a plus
• Hands-on background in DL/ML projects/programs is a plus.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.工作职责
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 30 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. We are now looking for Physical Design Engineer in Shanghai & Beijing office. What you’ll be doing: • Analysis on placement, routing, timing, clock, power, noise and DFM and provide optimization strategy • Work on full chip clock distribution • Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention. • Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.
• Work on flow enhancement of in-house flow on floorplan, power/clock distribution, placement, routing, timing/power/noise analysis, chip assembly, and physical verification • Work on in-house tool development and exploration • Look for AI solution to improve workflow efficiency and automation
• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • You will build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.
By submitting your resume, you’re expressing interest in one of our 2026 Hardware ASIC Design Internships. We’ll review resumes on an ongoing basis, and a recruiter may reach out if your experience fits one of our many internship opportunities. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society — from gaming to robotics, self-driving cars to life-saving healthcare, climate change to virtual worlds where we can all connect and create. Our internships offer an excellent opportunity to expand your career and get hands on experience with one of our industry leading Hardware teams. We’re seeking strategic, ambitious, hard-working, and creative individuals who are passionate about helping us tackle challenges no one else can solve.
• Chip integration and netlist generation • Synthesis, RTL/netlist quality check, Formal Verification • Constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure • Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation and method development • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Methodology and flow automation development for above areas.