英伟达Senior ASIC Engineer
任职要求
• BS / MS in electrical / computer engineering. • 3+ years working experience, with preference given to those with MS or equivalent experience. • Strong communication skills and proficient oral English since this role require frequent communication with external teams mainly in U…
工作职责
As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is essential in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed lower power/active power/thermal control logic. It collects and processes temperature, power, VR, and idle telemetries from the entire chip. It works with software on the RISC-V core to determine efficient operating points for different workloads on different chips. We are seeking a Senior ASIC Engineer who can help RTL coding or even architecting the next generation PMU for datacenter, GeForce, Auto, PC, Networking chips, etc. What you’ll be doing: • Collaborate with the production SW team and power arch team to define the architecture/micro-architecture for various power features. • Learn how PMU's function impacts the system and support the silicon debug. • Implement the micro-architecture to RTL design.
As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic. It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points. We are seeking a Senior ASIC Engineer who can help architect the next generation PMU for AI datacenter. What you’ll be doing: • Collaborate with the production SW team and power arch team to define the architecture/micro-architecture for various power features. • Learn how PMU's function impacts the system and support the silicon debug. • Implement the micro-architecture to RTL design.
• As a key MMPLEX Video Design team member, you will document, implement, and deliver fully verified, high-performance, low-area, and power-efficient designs to achieve the design targets and specifications. • Participate in video-related design and analyze architectural trade-offs based on features, performance requirements, and system limitations. • Craft micro-architecture, implement in HLS/RTL, and deliver a fully verified, synthesis/timing clean design. • Collaborate and coordinate with architects, other designers, pre- and post-silicon verification, SOCD, emulation, back-end, and bringup teams to accomplish your tasks.
• As a key MMPLEX Video Design team member, you will document, implement, and deliver fully verified, high-performance, low-area, and power-efficient designs to achieve the design targets and specifications. • Participate in video-related design and analyze architectural trade-offs based on features, performance requirements, and system limitations. • Craft micro-architecture, implement in HLS/RTL, and deliver a fully verified, synthesis/timing clean design. • Collaborate and coordinate with architects, other designers, pre- and post-silicon verification, SOCD, emulation, back-end, and bringup teams to accomplish your tasks.
• Understand the Switch architecture and data flows • Refine the full Chip working flow to improve the entire team's efficiency & smooth the project exeuction • Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW to meet project milestones.