英伟达Senior ASIC Engineer - Networking Chip Design
任职要求
• Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience • 3+ years of experience in ASIC frontend workflows o…
工作职责
• Understand the Switch architecture and data flows • Work in a combined design and verification team specializing in Switch Fullchip works, like assembly, integrations plus a series of QAs to ensure quality • Refine the full Chip working flow to improve the entire team's efficiency • Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW to deliver the FC model for project milestones.
• Understand the Switch architecture and data flows • Work in a combined design and verification team specializing in Switch Fullchip works, like assembly, integrations plus a series of QAs to ensure quality • Refine the full Chip working flow to improve the entire team's efficiency • Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW to deliver the FC model for project milestones.
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages