英伟达Circuit Calibration Methodology Engineer
任职要求
• MS with 6+ years or equivalent experience in Electrical Engineering (EE), Computer Engineering (CE), Computer Science (CS), Systems Engineering, or a related field • Deep understanding of analog/digital/mixed-signal circuit principles, including noise analysis, stability, and PVT variations • Experience in designing calibration hardware and software algorithms, integrating calibration routines into high-volume manufacturing test flows • Expertise in lab equipment (oscilloscopes, signal analyzers) and automated test systems (ATE) • Knowledge of statistical methods to optimize calibration processes and reduce measurement uncertainty • Experience in creating new system tests or automation tools, good skills in Linux, Python, and Perl. • Excellent problem solving, collaborative and interpersonal skills Ways to stand out from the crowd: • Background in pre-silicon/FPGA circuit feature validation, RTL design and …
工作职责
• Design architectures & algorithms for circuit calibration feature, characterize & model circuit behavior for both ATE and mission mode • Define circuit calibration software/firmware/tools, optimize calibration process and costs • Partner with ATE or SW team, integrate circuit calibration process into ATE or SW • Improve ATE to system correlation and circuit PVT variations
This role requires the familiarity of SMT test processes & its supply chain, the ability to work independently, good collaboration skills, and strong communications ability both in English and Mandarin. In this role, you will design & validate SMT test stations and constantly pursue new test methods as well as labor/cost reduction and automation. The testing engineering key functions will include: - Design for Testability: Collaborate with design team to generate ERS(engineering Requirements Specification) and ensure features are tested logically and efficiently. - Test Station Qualification: Collaborate with test station vendor to bring up test station and test coverage. Use statistical tools (such as GR&R, SPC, and Cp/Cpk) to ensure processes/fixtures are repeatable. - Failure/Data Analysis: Analyze tester related failures by deep dive in test theory/algorithm, define DOEs to figure out the root cause. Analyze test data to fine tune test spec, optimize test method and test time. You will travel (30%~50%) to both domestic and overseas' suppliers side for critical tasks.
THE ROLE As a power electronics engineer Intern, you will be a member of the world-class power electronics product design team to develop and test the high efficiency, high density and high reliability on-board battery charger. RESPONSIBILITIES Involve in performance calibration and testing of sub-circuits with alternative design. Efficiency, thermal, voltage stress analysis of the proposed new power conversion circuits. Circuit debugging of the root cause of the designed circuits. MATLAB modelling of the power conversion circuits modulation and operation.
• Architect essential next generation product features that are vital for performance, power optimization and management techniques all the way from feature definition to production; working with multi-functional teams. • Driving new feature initiatives across multiple business units, while translating noise aware circuits and performance requirements to hardware features, design requirements, silicon characterization needs and test requirements. Creating new system features and methodologies for Nvidia Silicon shipping into data center, consumer and automotive markets spanning broad areas. • Prototype and fine-tune the features on pre-production silicon fabricated using state-of-the-art processes for circuit, speed, performance, power, yield and quality to define the world’s fastest products. • Build pre and post-silicon methodologies to characterize Analog, digital and Mixed Signal circuits, silicon features, correlate silicon behavior with simulations, and provide design feedback. • Work alongside system architects, chip and board designers, software/firmware engineers, HW/SW applications engineering, process/reliability specialists, ATE engineers, product managers, sales, and operations, in a multifaceted, high-energy work environment to bring industry-defining products to market. • Designing tools to automate characterization, data collection, test case execution, and results analysis. • Find creative solutions to complex silicon and system level problems and be on the frontline to lead show-stopper bugs, in order to enable product shipment.
• Architect essential next generation product features that are vital for performance, power optimization and management techniques all the way from feature definition to production; working with multi-functional teams. • Driving new feature initiatives across multiple business units, while translating noise aware circuits and performance requirements to hardware features, design requirements, silicon characterization needs and test requirements. Creating new system features and methodologies for Nvidia Silicon shipping into data center, consumer and automotive markets spanning broad areas. • Prototype and fine-tune the features on pre-production silicon fabricated using state-of-the-art processes for circuit, speed, performance, power, yield and quality to define the world’s fastest products. • Build pre and post-silicon methodologies to characterize Analog, digital and Mixed Signal circuits, silicon features, correlate silicon behavior with simulations, and provide design feedback. • Work alongside system architects, chip and board designers, software/firmware engineers, HW/SW applications engineering, process/reliability specialists, ATE engineers, product managers, sales, and operations, in a multifaceted, high-energy work environment to bring industry-defining products to market. • Designing tools to automate characterization, data collection, test case execution, and results analysis. • Find creative solutions to complex silicon and system level problems and be on the frontline to lead show-stopper bugs, in order to enable product shipment.