AMDATE Engineer
任职要求
8-10 years’ industrial experience with >5 years test development experience Experience in digital product testing, good understanding of test method and IP, Scan/Bist/Func/HSIO/Fuse experience is preferred Advantest V93K, T2000, J750 popular …
工作职责
THE ROLE: ATE test program owner which owns wafer sort or final test insertion, developing and optimizing ATE test program for new coverage enhancement, test time reduction, new test method implementation, supporting production bring up, sustaining, issue debugging and continuous improvement for product indices. Working with regional teams extensively including product manager, project management, product engineering, DV, NPI, platform, software infrastructure team and hardware team on the test solutions optimization. THE PERSON: As the role of Test Engineer, we expect you could be self-motivation, creative thinking, and good communication skill in English KEY RESPONSIBILITIES: CPU test program owner in Asia, develop and release ATE test program production Early involvement in pre-silicon and silicon out phase including test coverage evaluation, pattern review, test flow development, test hardware design, charz and program release Develop engineering program to support various product engineering activities Post-production product new OPN enablement to support business needs Identify test time reduction opportunities and execute TTR for cost reduction Test program yield improvement via test debugging or test flow optimization Test issue debugging and solution providing with global cross functional team Other duties as assigned by supervisor
Product and Testing Engineer is in charge of memory product developments, including product validation & production testing flow definition, test method definition and implementation, device characterization, qualification and customer return material analysis. 2. Job Responsibilities 1) Owner of validation & production testing, characterization, qualification and customer return material analysis. 2) Define characterization, qualification and mass production test methodologies. 3) Be responsible of memory product test program development and validation on varies test platforms. Ensure delivery of test program in time. 4) Be responsible for failure analysis and investigation of customer device/application issue during product development phase. 5) Identify device failure mechanism through electrical failure analysis, and support physical failure analysis during development and product development phase. 6) Support testing platform development with HW design engineers. 7) Support mass production yield improvement, TTR and DPPM reduction. 8) Support other teams, such as design team, PIE, RE required DOEs.
Wafer Sort Testing Engineer is in charge of wafer level memory product developments, including wafer level validation & production testing flow definition, test method definition and implementation, wafer level memory device characterization, qualification and customer return material analysis. Deliver qualified product to mass production as well as sustaining product for wafer level yield improvement, TTR and DPPM reduction. 2. Job Responsibilities 1) Owner of wafer level validation & production testing, characterization, qualification and customer return material analysis. 2) Define wafer level characterization, qualification and mass production test methodologies. 3) Be responsible of wafer level memory product test program development and validation on varies test platforms. Ensure delivery of test program in time. 4) Be responsible for wafer level test failure analysis and investigation of customer device/application issue during product development phase. 5) Identify device failure mechanism through electrical failure analysis, and support physical failure analysis during development and product development phase. 6) Support testing platform development with HW design engineers. 7) Support wafer level mass production yield improvement, TTR and DPPM reduction. 8) Support other teams, such as design team, PIE, RE required DOEs.
Wafer Sort Testing Engineer is in charge of wafer level memory product developments, including wafer level validation & production testing flow definition, test method definition and implementation, wafer level memory device characterization, qualification and customer return material analysis. Deliver qualified product to mass production as well as sustaining product for wafer level yield improvement, TTR and DPPM reduction. 2. Job Responsibilities 1) Owner of wafer level validation & production testing, characterization, qualification and customer return material analysis. 2) Define wafer level characterization, qualification and mass production test methodologies. 3) Be responsible of wafer level memory product test program development and validation on varies test platforms. Ensure delivery of test program in time. 4) Be responsible for wafer level test failure analysis and investigation of customer device/application issue during product development phase. 5) Identify device failure mechanism through electrical failure analysis, and support physical failure analysis during development and product development phase. 6) Support testing platform development with HW design engineers. 7) Support wafer level mass production yield improvement, TTR and DPPM reduction. 8) Support other teams, such as design team, PIE, RE required DOEs.
1.新产品良率电性测试分析, 根据测试诊断确认电性失效模型. 2.新产品功能验证,参数特性测试验证, 推动 Design, Device, PIE, PE 进行参数优化调整 3.测试程式编写以及优化，新测试方案以及模式开发以辅助产品失效分析