AMD数字后端实习生 Physical Design Intern (Jan - Jun 2026)
任职要求
Strong scripting skill like python/perl/tcl is preferred. Strong knowledge of analog IP design or process like working experience in foundry is preferred. Optional for knowledge and hands-on experience of entire design process including synthesis, block level (full chip) floor planning, timing budget, place&route, timing closure, power analysis physical verification etc Must have good communication & analytical thinking skills, should be able to work closely with FEI, DFT team and other Physical Design teams across multiple sites. Should have expertise in: Calibre, ICC2, Primetime, Redhawk #LI-EJ1
工作职责
An exciting internship opportunity to make an immediate contribution to AMD's next generation of technology innovations awaits you! We have a multifaceted, high-energy work environment filled with a diverse group of employees, and we provide outstanding opportunities for developing your career. During your internship, our programs provide the opportunity to collaborate with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more. Being part of AMD means receiving hands-on experience that will give you a competitive edge. Together We Advance your career! JOB DETAILS: THE ROLE: Work with talented colleague cross different sites in different countries, to achieve a goal of tapeout on time after all needed sign-off checks. You will be in key position of handling quality of gds delivered to foundry and AMD will provide you a great platform of learning most advanced silicon technologies and exhibiting your excellent skill and personalities. THE PERSON: Given that you will work with teams abroad, English communication skill is a must and team work is also important for our daily work. As a plus, dedicated and innovative sprit is welcomed. KEY RESPONSIBILITIES: Focus on physical verification like DRC, LVS, Antenna, ESD, Latch-up, PERC checks in projects to ensure allocated work can be done within target timeline, to finally make sure tapeout on time. Have chance to learn all PhyV related knowledge and thus have a clear overview of how a large SOC works and how it pass all required verifications till a successful tapeout. Will have chance to exhibit your innovative ideas of enhancing current work flow or creating new tools/flow to automate daily work to increase efficiency.
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