AMDSilicon Design Engineer
任职要求
Proven understanding of RTL design, synthesis, and ECO principles Excellent knowledge with FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, PtPx, etc. Proficient with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile) Excellent skills with Unix/Linux environment Familiar with RTL coding techniques for competitive PPA-measured QoR Familiar with RTL coding style for clean check on design rules (LINT, CDC, etc.) Good understanding of gate level circuit design and physical level design concept and methodology Familiar with VCS/Verdi Excellent communication skills in English (both written and oral) Self motivated, and committed to achievement ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-EH1
工作职责
THE ROLE: A Front-End Silicon Design and Integration (FEINT) Engineering role in our GFX Memory Controller IP (GMCIP) team. GFX Memory controller provides high performance functions to System on Chip (SoC) products across all AMD business units such as GPU AI accelerators, graphics and gaming. Our FEINT engineers will perform RTL synthesis and PPA analysis in order to improve the QoR of RTL designs. They will also create, adopt and automate RTL static design rule checks, perform ECO and LEC checks. THE PERSON: A talented FEINT engineer with strong records of technical ownership and execution to drive synthesis, PPA analysis, Power redux, ECO, and static verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. KEY RESPONSIBILITIES: Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result) Develop power redux strategy such as hierarchical CG (clock gating) at multiple levels including RTL and gate level, to ensure power target attainment Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies Develop, adopt and automate RTL static design rule checks in collaboration with Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team Develop and adopt FEINT design and verification infrastructure, methodology and tools
THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
THE ROLE: The focus of this role is to plan, build, and execute the design of new and existing features for AMD’s FCH IP (involving management of system power states, reset, clocking as well as some sub-IP controllers), resulting in no bugs in the final design. It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM architecture, AMBA(AXI/AHB/APB) bus, USB(4.0/3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/eSPI/GPIO), General connectivity IPs (I2C/I3C/UART), Ethernet, JTAG, etc.
THE ROLE: This is a role in post-silicon power and performance engineering team who will act as end-to-end owner for System/APU/GPU performance optimization from first silicon to production. This role needs to have stronger data scientific sense which can learn and build power and performance data insight structure via well-using internal experiment data including the whole data analytic process from data collecting, clean, modelling , templating, insights, and visualization. Technically it requires the person to have a clear understand of key performance influence factors in silicon design and implementation, also understand how to collaborate with the critical program milestone and be responsible to drive across sites and across teams for performance related feature readiness and data analytics. THE PERSON: The person needs to be passionate and well self-motivated, sensitive to the delivery urgency and the innovation path, a good communicator with teamwork spirit, eager to learn new knowledge, able to resolve complex problem. The person needs to have a natural interest in mathematic algorithms, logical coding and beauty of data telling. The person needs to be enthusiasm on data analytic job. KEY RESPONSIBILITIES: Work closely with internal data producing team and external automation framework team to develop engineering experience-based power and performance data analytic process and visualization structure. Work closely with SOC design team & program lead team to understand performance target and validation methodology for APU/GPU Component and overall reference design System Develop system and component level performance test strategies and plans. Attend ASIC bring-up and validation, ensure coverage and schedule. Execute performance test plans for APU/GPU/System and give out the improvement suggestion. Compose validation reports and provide future test plan improvement. Work with CE team to understand Customer expectations of power and performance design and support debugging. Automate some of manual tests in Shell/Python or other scripting language.
An exciting internship opportunity to make an immediate contribution to AMD's next generation of technology innovations awaits you! We have a multifaceted, high-energy work environment filled with a diverse group of employees, and we provide outstanding opportunities for developing your career. During your internship, our programs provide the opportunity to collaborate with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more. Being part of AMD means receiving hands-on experience that will give you a competitive edge. Together We Advance your career! JOB DETAILS: Location: Shanghai Onsite/Hybrid: This role requires the student to work onsite at least 3 days/week throughout internhsip Duration: Jan - Jun 2026 WHAT YOU WILL BE DOING: We are seeking highly motivated Silicon Design Engineer Engineering intern/co-op to join our team. In this role – RTL implementation Collaborate with verification team to achieve good coverage RTL based power, timing and area tracking/analysis