AMDSilicon Design Engineer

负责Foundry工艺Model的分析、QA以及Model的优化，并能够和供应商合作针对特定产品提出定制化的建议和解决方案，具体职责如下： 1. Foundry model全面性分析和QA、Model和Silicon 比对和PPA 分析。 2. Designer 设计过程Model相关问题的支持和沟通，并和designer合作给出产品Signoff建议。 3. 定制Engineer Model 的合作开发以及支持，包括相关Testkey设计和数据分析。 4. 有Foundry Model TK设计、数据收集以及Model开发经验或Design House Model定制以及应用相关经验为佳。

In this role, you will work with software and hardware engineering groups to define the cutting edge of next-generation AI SOC chips for high-performance computing platform in Data Center. * as a design engineer, strong coding skill of system Verilog or Verilog to implement RTL design, develop SOC domain system/interface IP for various SOCs * familiar with ASIC flow to create complex SOCs with advanced methodologies more efficient, participated 3rd party IP integration * strong problem solving and solution for SOC design and IP integration, timing closure, silicon bring up and issue debug * Documents the high-level architecture specification that defines the chip with various sub-systems for the cutting-edge cloud applications. * Works closely with PD, power, system, and verification team to bring up the subsystem

In this role, you will work with software and hardware engineering groups to define the next-generation inter-chip network architecture for high-performance computing SOC in Data Center Requirement of the Job * Identifies the challenging problems, and evaluate the various solutions for next-generation data center Computing solutions. * Gets strong influences on the shape of future products by advanced architecture design as the excellent interface between software and hardware * Documents the high-level architecture specification that defines the inter-chip network subsystem for the cutting-edge cloud applications. * Works closely with design, system, and verification team to bring up the subsystem

As a member of the DFP (Design For Power) team you will be responsible for developing and defining low power implementation and EMIR signoff methodology of world class chips under most advanced tech node. Your responsibilities may include, but not be limited to: · Developing physical design flow which including the construction of power delivery network, building of multi-voltage and power gating design, power aware optimization etc. · Defining EMIR signoff methodology at block & chip level, including signoff corner, analysis condition, signoff target and criteria etc. Conducting hotspot/grid weakness study and providing improvement plan · Engaging closely with front-end power team on power estimation and fullchip power budgeting · Working closely with package/PISI team for system level IR convergence for all analog/digital domains and be the 'go-to' person for cross team deliverables · Driving low power design and verification closure by engaging with design/synthesis teams on optimizing chip power structure and power intent to manage physical design risks · Working with EDA vendors to resolve tool issues and drive improvements in design convergence and signoff · Leading full chip EMIR sign-off, monitor EMIR status and manage risks at each milestone to meet tapeout schedule · Driving silicon correlation with a continuous plan to optimize timing/EMIR signoff margin · Empowering physical design engineers to create industry leading chips by providing guidelines on PPA improvement plan from DFP perspective