AMDSilicon Design Engineer
任职要求
As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: PRIMARY RESPONSIBILITY: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications Perform RTL design integration, inserti…
工作职责
THE ROLE: Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. It is also responsible for DFx design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.
-在芯片设计阶段，从系统应用和调试角度参与芯片定义 -结合业界标准规范和实际应用场景制定全面详细的validation plan -在post silicon阶段，负责芯片的bring-up和validation，分析并解决在此过程中发现的问题 -开发validation和debug所需的测试工具和脚本 -与软硬件团队合作，基于主流AI模型，进行系统性能和功耗以及稳定性的分析与优化 -在芯片量产落地阶段，负责分析并解决生产侧、服务器适配侧以及客户侧遇到的硬件和系统级问题
1、负责芯片底层软件开发和SoCBring-up; 2、负责SoC芯片的软件验证，包括Pre-silicon和Post-silicon阶段的验证； 3、负责BootRom/SoC底软开发&交付工作（MSCP/Tiano/UBoot/Coreboot/LinuxBoot/TF-A/TF-M/OpenSBI）； 4、负责Core/NOC/UCIe/PCIe/DDR/PMU/RAS等某一IP的Firmware/Driver开发； 5、负责SoC HSM/Secure Boot/TF-A/TEE OS等软件开发；负责SoC Cypto engine/安全Driver等功能开发和验证； 6、负责NIC、DPU及RDMA硬件驱动开发、特性使能以及业务场景落地。
1. 配合算法部门进行定点化及资源、架构优化，对交付的4/5G通信IP的定点化算法进行芯片架构设计及后续RTL设计和IP交付 2. 确保前端交付的各项质量检查 3. 和验证等团队协作，完成功能及时序验证 4. 和中后端团队协作，完成通信IP的物理实现及交付 5. 与其他团队合作，完成功耗、面积、性能的评估。 6. 支持软件等相关团队完成FPGA&post silicon的测试及量产工作。
一、 岗位职责 1. 负责数字芯片系统设计。 2. 负责数字芯片IP设计。 3. 和其他团队协作，完成功能验证/时序实现 以及 post silicon的测试工作。 4. 与其他团队合作，完成功耗、面积、性能的评估。 5. 确保前端交付的各项质量检查。