AMDProduct Development Engineer-ATE

Product and Testing Engineer is in charge of memory product developments, including product validation & production testing flow definition, test method definition and implementation, device characterization, qualification and customer return material analysis. 2. Job Responsibilities 1) Owner of validation & production testing, characterization, qualification and customer return material analysis. 2) Define characterization, qualification and mass production test methodologies. 3) Be responsible of memory product test program development and validation on varies test platforms. Ensure delivery of test program in time. 4) Be responsible for failure analysis and investigation of customer device/application issue during product development phase. 5) Identify device failure mechanism through electrical failure analysis, and support physical failure analysis during development and product development phase. 6) Support testing platform development with HW design engineers. 7) Support mass production yield improvement, TTR and DPPM reduction. 8) Support other teams, such as design team, PIE, RE required DOEs.

Wafer Sort Testing Engineer is in charge of wafer level memory product developments, including wafer level validation & production testing flow definition, test method definition and implementation, wafer level memory device characterization, qualification and customer return material analysis. Deliver qualified product to mass production as well as sustaining product for wafer level yield improvement, TTR and DPPM reduction. 2. Job Responsibilities 1) Owner of wafer level validation & production testing, characterization, qualification and customer return material analysis. 2) Define wafer level characterization, qualification and mass production test methodologies. 3) Be responsible of wafer level memory product test program development and validation on varies test platforms. Ensure delivery of test program in time. 4) Be responsible for wafer level test failure analysis and investigation of customer device/application issue during product development phase. 5) Identify device failure mechanism through electrical failure analysis, and support physical failure analysis during development and product development phase. 6) Support testing platform development with HW design engineers. 7) Support wafer level mass production yield improvement, TTR and DPPM reduction. 8) Support other teams, such as design team, PIE, RE required DOEs.

Wafer Sort Testing Engineer is in charge of wafer level memory product developments, including wafer level validation & production testing flow definition, test method definition and implementation, wafer level memory device characterization, qualification and customer return material analysis. Deliver qualified product to mass production as well as sustaining product for wafer level yield improvement, TTR and DPPM reduction. 2. Job Responsibilities 1) Owner of wafer level validation & production testing, characterization, qualification and customer return material analysis. 2) Define wafer level characterization, qualification and mass production test methodologies. 3) Be responsible of wafer level memory product test program development and validation on varies test platforms. Ensure delivery of test program in time. 4) Be responsible for wafer level test failure analysis and investigation of customer device/application issue during product development phase. 5) Identify device failure mechanism through electrical failure analysis, and support physical failure analysis during development and product development phase. 6) Support testing platform development with HW design engineers. 7) Support wafer level mass production yield improvement, TTR and DPPM reduction. 8) Support other teams, such as design team, PIE, RE required DOEs.

This is a summer Internship program for graduates from Oct, 2025 to Nov. 2026. Interview progress will start from the week of 10th, Mar.欢迎2025年10月至2026年11月毕业的同学加入TI暑期实习项目。面试将于3月10日正式开启。    Change the world. Love your job. The Validation/Characterization Engineering Intern at Texas Instruments are powered by a passion for continual improvement. Our solutions make a real difference and yours will, too. We make the semiconductor product design process easier and faster, which helps our customers succeed in today's fast-paced marketplace. In this role, you'll support the development and implementation of strategies that achieve profitability targets on assigned TI product lines through new product development, cost reduction, capacity expansion and yield enhancement projects. You'll serve in development and implementation of cost-effective analog test techniques, resolve customer quality and application issues, and facilitate cross-functional teams for problem solving. You will collaborate with Analog Design on design-for-test features and Applications team on validation, while also tackling challenging problems in achieving analog performance testing on ATE multi-site hardware. These teams develop differentiating innovations in the test domain, ranging from methods to lower test cost for TI without compromising quality, to identifying design improvements for test, and resolving complex technical problems requiring an individual to transcend multiple domains.