IBMSystems Z Software Brand Sales Specialist

THE ROLE:  As a Server Customer Platform Application Engineer, you are responsible for customer server system development program technical support from concept to end of life. This includes concept design, schematic and layout review, signal integrity and power in-tegrity, electrical validation, system integration, manufacture, etc. You will provide technical support across platform design, platform debug and system validation to meet program goals of quality platform delivery on schedule at target performance.   THE PERSON:  As a Server Customer Platform Application Engineer, you must have experience as a domain expert in at least one or more areas include system design, schematic, layout, SI/PI, EV, validation and have basic understanding of the general system design process (preferably Server), from concept to gerber-out and through production.   KEY RESPONSIBILITIES:  Work with MDC/OEM/ODM partners to enable successful deployment of AMD server platforms by augmenting customer solutions with technical collateral including whitepaper, application note, user guide on customization and tuning, reference design materials, and debugging/profiling toolsPerform design reviews include concept, block-level, schematic, layout for customer platorms and/or referene platformsSupport bring-up, validaiton and debug of platform related issuesEngage directly on key technical topics, issues, architecture discussions, deisgn optimizations with customers and internal teams and steer of multi-party disscussion to convergenceAnalytic ability to address technical issues and generate creative solutionsOn-site support to speed up issues closure to meet overall project schedule  PREFERRED EXPERIENCE:  3+ years of server/client SOC or system development experienceBoard Design Fundamentals pertaining to Mixed signal design, High Speed board design, and Power DesignHands-on with debug, triage, and validation procedures for all the interfaces and subsystems of a platformExperience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.  Knowledge of server system architecture, technical debug, and validation strategyFair knowledge of HW development life-cycle end to end from Design Conception, Execution, Fabrication & Assembly, board Bring-up, Test & Validation, Reporting and Customer support.  ACADEMIC CREDENTIALS:  Bachelors and/or higher degree in EE/CS or related majors #LI-CC1

THE ROLE: This is a role in post-silicon power and performance engineering team who will act as end-to-end owner for System/APU/GPU performance optimization from first silicon to production. This role needs to have stronger data scientific sense which can learn and build power and performance data insight structure via well-using internal experiment data including the whole data analytic process from data collecting, clean, modelling , templating, insights, and visualization. Technically it requires the person to have a clear understand of key performance influence factors in silicon design and implementation, also understand how to collaborate with the critical program milestone and be responsible to drive across sites and across teams for performance related feature readiness and data analytics. THE PERSON: The person needs to be passionate and well self-motivated, sensitive to the delivery urgency and the innovation path, a good communicator with teamwork spirit, eager to learn new knowledge, able to resolve complex problem. The person needs to have a natural interest in mathematic algorithms, logical coding and beauty of data telling. The person needs to be enthusiasm on data analytic job. KEY RESPONSIBILITIES: Work closely with internal data producing team and external automation framework team to develop engineering experience-based power and performance data analytic process and visualization structure. Work closely with SOC design team & program lead team to understand performance target and validation methodology for APU/GPU Component and overall reference design System Develop system and component level performance test strategies and plans. Attend ASIC bring-up and validation, ensure coverage and schedule. Execute performance test plans for APU/GPU/System and give out the improvement suggestion. Compose validation reports and provide future test plan improvement. Work with CE team to understand Customer expectations of power and performance design and support debugging. Automate some of manual tests in Shell/Python or other scripting language.

THE ROLE: Processor silicon DDR interface feature enable, electrical test and debug engineer. In this role, this senior level engineer will be part of a highly technical team that develops test plans, executes bring-up & feature enable, & debugs electrical issues in the memory sub-system of new processors.

THE ROLE:  Work closely with MDC/OEM/ODM partners to enable successful deployment of AMD server platforms by augmenting customer solutions with technical collateral, such as application note documentation, user guide on customization and tuning, sample and reference design materials, and debugging/profiling tools Perform bringing up support, as well as debugging on internal and external reference and production designs, and provide solutions to customers Engage directly on key technical topics, issues, architecture discussions, and performance optimizations with customers and internal teams and steer of multi-party discussion to convergence Analytic ability to address technical issues and generate creative solutions On-site support to speed up issue closure to meet overall project schedule