长江存储Digital Design Engineer(J13709)
任职要求
- BS or MS in electric and electronic engineering； - Relevant experience in Flash memory design a plus; - Relevant experience in near memory computing a plus; - Skills of Verilog RTL coding, simulation debug and base or me…
工作职责
- Write Micro-Architecture Definition/Writing Design Implementation Spec based on Flash memory feature requirements； - Write RTL coding for block or top level； - Do IP level synthesis / timing analysis / formality check / CDC check /Code coverage check； - Assist on Verification Engineer to complete module and top level simulation and verification; - Debug RTL/Gate Level waveform at module or top level; - Do Silicon debugging of the related module functionalities and provide ECO solution accordingly；
THE ROLE: The focus of this role is to plan, build, and execute the design of new and existing features for AMD’s FCH IP (involving management of system power states, reset, clocking as well as some sub-IP controllers), resulting in no bugs in the final design. It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM architecture, AMBA(AXI/AHB/APB) bus, USB(4.0/3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/eSPI/GPIO), General connectivity IPs (I2C/I3C/UART), Ethernet, JTAG, etc.
SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.
THE ROLE: AMD CAD team is part of Central Design Methodology team and be responsible to deliver differentiated ASIC implementation flows (from RTL to GDSII) for all AMD products. You'll be working with the global CAD team on synthesize flows.
MTS SILICON DESIGN ENGINEER THE ROLE: CIT (Chiplet Interconnect Technology) tam delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. As the team member, you will have access to cutting-edge technology/tools/process, all stages of functional verification on CIT IP, including test plan & test development, regressions, and infrastructure development.