长鑫存储工艺整合课经理 I Process Integration Section Manager(J15444)
任职要求
1.半导体或物理与材料科学专业硕士背景，8年以上工作经验，其中2年管理经验； 2.PIE、DEFECT、METRO、DEVICE、YE、精通任一Module PE相关方向经验均可，具有DRAM和TD经验者优先； 3.具备良好的领导能力和与跨部门的沟通技巧； 4.技术问题决策，并具备出色的领导团队快速解决问题的能力； 5.熟悉Fab/TD流程，具备良好的项目管理技能； 6.熟悉技术转移，了解研发转量产全流程。
工作职责
1.To manage integration of all modules’ processes and the respective derivatives; 2.To provide a leading role in the developing, transferring and maintaining of advanced DRAM fabrication technology with good process capability and high yield.Lead new technology transfer from mother fab or process development; 3.Owner of new prototype lots and ensure 100% success rate; 4.Drive process robustness improvement by providing root cause analysis and and collaborate improvement actions to meet 100% wafer acceptance test (WAT) Cpk goal & Baseline D0 target.
1. 根据公司MBO，带领团队完成组织目标分解及达成；能够提供问题解决的整体思路和外部资源协调 2. 熟悉DRAM Process flow, 对每个loop都有一定理解,带领团队维持制程制产线稳定，提升产品良率; 3. 与客户沟通解决产品端问题，横向拉通 业务所需的相关部门，助力客户产品保质保量完成 5.建设人才梯队, 标准化各类业务流程。
1. 根据公司MBO，完成组织目标分解及达成； 2. 带领团队对CMP各道工艺的优化/维持/改善/规划，降低缺陷率 & 良率提升； 3. 开发2nd Source & 制定完整执行计划, 降低成本； 4. 进行跨部门沟通协调，工作优先顺序 & 内外资源的协调合作； 5. 人才培养, 标准化各类流程。
1.熟悉半导体研发工艺和产品流片过程 2.制定、创新工艺制程方案，发现并解决在线工艺问题，协调各个部门提出解决方案，确保产品的进程 3.能够处理在线实验产品，及时应对突发状况，针对测试流片的结果对工艺过程、线上参数、电性、可靠性、良率写总结报告 4.熟悉NAND、NOR、CMOS器件原理，理解版图设计规格，设计测试图形，定期分析WAT参数、良率、可靠性，制定改善措施以优化工艺过程，提高产品良率 5.实施产品流片，制定管控计划，数据收集，问题改善等 6.整合各部门资源，提升工艺技术、产品良率、产品质量及成本效率
1.Be responsible for the design and development of the device architecture of 3D NAND Flash, and deeply participate in the whole process from concept design to mass production. Utilize professional knowledge to carry out innovation at the architecture level, optimize the structure of memory cells, and improve storage density, performance and reliability. 2.Collaborate with the circuit design team to complete the efficient transformation from device physical characteristics to circuit logic, ensuring the compatibility and performance of the overall system. And increase the read and write speed and reduce power consumption. 3.Lead the research and application of new technologies, explore cutting-edge fields such as new materials and manufacturing processes, and provide technical support for the performance breakthrough of 3D NAND Flash. Through the research on industry trends, promote technological innovation and enhance product competitiveness. 4.Conduct in-depth analysis of the problems in the R&D process by using the knowledge of device physics and semiconductor processes, and put forward effective solutions. Use data analysis and modeling techniques to optimize device performance and ensure that products meet high-quality standards. 5.Lead/Participate in test chip tapeout for new memory technology development and product chip tapeout for production introduction 6.Interact with process module, material, simulation, device characterization and reliability group to optimize process flow, improve memory cell device performance and develop innovative solution to meet product requirement and qualification criteria 7. Drive cross-functional team including process module, device, product engineering, design, YE, YAE, TO, and Test to address process/technology gap and yield/margin issues