平头哥平头哥-芯片STA资深工程师/专家-上海
任职要求
The ideal candidate should exhibit behavioral traits that indicate: • Self-motivator with strong problem-solving skills • Excellent interpersonal skills, including written and verbal communication • Ability to work as part of a team and collaborate in a high-paced atmosphere • Ability to provide technical direction to the team and influence project execution and methodology Qualifications • Mtech/Btech Engineering Degree in field of Electrical, Electronics, Computer Science with 2+/10+ yrs of relevant RTL2GDS experience • Demonstrate…
工作职责
In a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be responsible for leading and defining timing signoff design methodologies of complex and world class chips/IPs. In this position, your responsibilities may include, but not be limited to: • Defining and implementing signoff methodology for all areas related to timing analysis, Circuit Quality, Extraction and noise glitch analysis； • Developing robust ASIC design and verification methodology to meet performance requirements including PVT corner definition for design convergence, clock uncertainty requirements, timing budgeting, repeater planning, automatic constraints/exceptions generation & management, and other key differentiating capabilities for quality & efficient timing closure； • Working closely with process technology team to understand process characteristics and setting appropriate design constraints to model on-chip variation effects, power-supply variation, process aging and other PV/Si miscorrelation effects in timing analysis flows； • Engaging closely with Design teams to understand the design & convergence challenges and derive methods to provide recipes with a focus on PPA & TAT optimizations； • Developing timing flows, understand design requirements/objectives and develop signoff conditions and milestone checklists appropriate with the design project goals. Work with 3rd party EDA vendors to resolve issues and drive improvements in design convergence and signoff； • Lead full chip timing signoff work, including SDC quality check, timing aware physical implementation guide, timing analysis and signoff.
In a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be responsible for leading and defining timing signoff design methodologies of complex and world class chips/IPs. In this position, your responsibilities may include, but not be limited to: • Defining and implementing signoff methodology for all areas related to timing analysis, Circuit Quality, Extraction and noise glitch analysis； • Developing robust ASIC design and verification methodology to meet performance requirements including PVT corner definition for design convergence, clock uncertainty requirements, timing budgeting, repeater planning, automatic constraints/exceptions generation & management, and other key differentiating capabilities for quality & efficient timing closure； • Working closely with process technology team to understand process characteristics and setting appropriate design constraints to model on-chip variation effects, power-supply variation, process aging and other PV/Si miscorrelation effects in timing analysis flows； • Engaging closely with Design teams to understand the design & convergence challenges and derive methods to provide recipes with a focus on PPA & TAT optimizations； • Developing timing flows, understand design requirements/objectives and develop signoff conditions and milestone checklists appropriate with the design project goals. Work with 3rd party EDA vendors to resolve issues and drive improvements in design convergence and signoff； • Lead full chip timing signoff work, including SDC quality check, timing aware physical implementation guide, timing analysis and signoff.
The candidate is expected to be responsible for following tasks: - Participate in complex Chip DFT/DFD feature and architecture definition - Implement DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic - Generate DFT related timing constraints and work for timing closure - Develop and verify high coverage and cost effective test patterns for the production test - Design, implement and verify other DFX (debug, characterization, yield etc) feature - Evaluate and establish the advanced DFT/DFD tools and flow as DFT CAD
1、主导SOC芯片的定义，主导和参与产品关键场景的设计、实现和验证，负责技术体系的搭建； 2、主导SOC软件的需求分析、架构设计和方案分析，输出需求规格，子系统架构、系统分析文档，参与技术评审与决策； 3、洞察行业内软硬件技术驱动，研究软硬件前沿技术，输出领域技术规划，推动软硬件协同设计； 4、主导某一领域的技术发展，包括性能领域、功耗领域、安全领域、低功耗智能领域、DFX领域、套片软件，软件架构、软件工程等领域。
1、负责内存芯片（System Cache、SMMU、DDR）及存储器模块的架构设计、优化和性能提升； 2、负责内存管理以及子系统优化，负责多媒体领域内存管理（包含性能优化、内存容量管理等）和性能优化； 3、负责文件系统、老化等系统分析、设计和优化，提升系统性能； 4、洞察行业内存存储技术，研究软硬件前沿技术，输出领域技术规划，推动软硬件协同设计。