平头哥平头哥-芯片可靠性测试验证专家/高级专家-深圳
任职要求
1.材料学、固态电子学、电子相关专业硕士及以上学历
Master degree or above on material science, solid-State Electronics, and electronics related.
2.3年以上可靠性测试验证经验，熟悉可靠性测试验证工作，包括但不限于环境可靠性实验、老化测试实验等，有可靠性验证方案开发、向量开发、老化测试机台调试经验者优先
3+ years’ experience in reliability testing and verification, familiar with reliability te…工作职责
芯片产业进入后摩尔时代，芯片封装解决方案面临诸多挑战。封装的尺寸、结构、散热、BOM材料、制造工艺，共同影响芯片的性能、成本、以及应用可靠性。作为封装工程师，你将致力于业界最高端芯片封装解决方案的设计、开发、制造、测试、验证，失效分析以及技术创新。在这里，你可以了解并获得最先进的芯片封装技术知识及能力，并和业界顶尖的工程师一起，共同开发最先进封装技术，并推动其持续发展。 As IC industry enters the more than Moore era, chip packaging solutions are facing many challenges. Package size, package structure, heat dissipation, BOM material, and manufacturing process all affect chip performance, cost, and application reliability. As a packaging engineer, you will be dedicated to the design, development, manufacture, testing, verification, failure analysis, and technological innovation of the industry's highest-end chip packaging solutions. Here, you can understand and acquire the relevant knowledge and skills of the most advanced chip packaging technology, and work with the industry's top engineers to jointly develop the most advanced packaging technology and promote its continuous development. 工作职责RESPONSIBILITIES: 作为可靠性测试验证工程师，负责IC可靠性测试方案的制定与设计，保证芯片可靠性测试验证的顺利开展以支撑芯片及产品的开发及量产应用 Work as a Reliability Test and Verification Engineer, define reliability solution and its corresponding hardware design, to ensure reliability test and verification tasks to support the development and mass production of chips and products. 负责芯片及产品相关的失效分析、可靠性寿命评估，并针对失效分析结果联合上下游团队提出适当的解决方案 Responsible for failure analysis and reliability life assessment to chips and products, and work with up/down-stream teams to propose appropriate solutions based on failure analysis results 构建并不断完善可靠性测试流程、系统，支撑公司产品交付 Build and continuously improve the reliability test process and system to support the company's product delivery 从效率、成本等角度对可靠性测试方法、方案开展持续改进及优化，保证产品测试质量的基础上，不断提升可靠性测试竞争力 Continuous improvement and optimization of reliability test methods and solutions from the perspectives of efficiency and cost, and continuously improve reliability test competitiveness on the basis of ensuring product test quality. 跟踪行业技术趋势，开展可靠性寿命评估模型及方法的研究，应对新工艺制程、新结构、新材料的挑战 Track on the industry trend, perform research on reliability life assessment models and methodology, to addressing challenge on new process, new structure and new material.
芯片产业进入后摩尔时代，芯片封装解决方案面临诸多挑战。封装的尺寸、结构、散热、BOM材料、制造工艺，共同影响芯片的性能、成本、以及应用可靠性。作为封装工程师，你将致力于业界最高端芯片封装解决方案的设计、开发、制造、测试、验证，失效分析以及技术创新。在这里，你可以了解并获得最先进的芯片封装技术知识及能力，并和业界顶尖的工程师一起，共同开发最先进封装技术，并推动其持续发展。 As IC industry enters the more than Moore era, chip packaging solutions are facing many challenges. Package size, package structure, heat dissipation, BOM material, and manufacturing process all affect chip performance, cost, and application reliability. As a packaging engineer, you will be dedicated to the design, development, manufacture, testing, verification, failure analysis, and technological innovation of the industry's highest-end chip packaging solutions. Here, you can understand and acquire the relevant knowledge and skills of the most advanced chip packaging technology, and work with the industry's top engineers to jointly develop the most advanced packaging technology and promote its continuous development. 工作职责RESPONSIBILITIES: 作为可靠性测试验证工程师，负责IC可靠性测试方案的制定与设计，保证芯片可靠性测试验证的顺利开展以支撑芯片及产品的开发及量产应用 Work as a Reliability Test and Verification Engineer, define reliability solution and its corresponding hardware design, to ensure reliability test and verification tasks to support the development and mass production of chips and products. 负责芯片及产品相关的失效分析、可靠性寿命评估，并针对失效分析结果联合上下游团队提出适当的解决方案 Responsible for failure analysis and reliability life assessment to chips and products, and work with up/down-stream teams to propose appropriate solutions based on failure analysis results 构建并不断完善可靠性测试流程、系统，支撑公司产品交付 Build and continuously improve the reliability test process and system to support the company's product delivery 从效率、成本等角度对可靠性测试方法、方案开展持续改进及优化，保证产品测试质量的基础上，不断提升可靠性测试竞争力 Continuous improvement and optimization of reliability test methods and solutions from the perspectives of efficiency and cost, and continuously improve reliability test competitiveness on the basis of ensuring product test quality. 跟踪行业技术趋势，开展可靠性寿命评估模型及方法的研究，应对新工艺制程、新结构、新材料的挑战 Track on the industry trend, perform research on reliability life assessment models and methodology, to addressing challenge on new process, new structure and new material.
候选人主要从事的工作是高性能计算相关的模拟接口IP的研发，包括不限于D2D/Memory/C2C/板卡互联等。候选人需要完成IP的立项、架构、交付、开发、测试等端到端的工作，需要具备如下能力至少一项（第4项为必备项）： 1.IP立项：可以完成IP 的竞争力分析，确定IP 的长期演进技术方向，并完成IP 架构选型、关键技术分析、竞争力构建策略；主导IP 立项。 2.IP架构：完成IP 架构的建模、指标分解、具体电路的方案调研，并跟踪电路的开发，确保指标达成和竞争力的实现。 3.IP 交付：需要熟悉数模混合IP交付的流程，可以配合封装、测试、模型、算法、数字设计、数字验证完成模拟IP 相关交付件的需求梳理、交付件对齐、数模混合验证等工作。 4.IP 开发：需要至少CMU（时钟管理单元）、TX、RX 一个领域有深入的理解，可以选择适配IP 的最有竞争力的方案；并完成组件的设计、指导CL布局布线、 仿真验证等。 5.IP 测试：完成测试需求的收集、评审；测试用例的完备性分析；测试方案的开发和验证；回片的测试的启动和测试问题的攻关。
1. 负责智算高性能存储系统架构设计与开发，面向AI训练场景的高性能并行文件系统模块开发，设计多级元数据服务架构，支撑海量文件与高吞吐数据流。 2. 软硬件定义，机型设计，构建存算协同机制，实现GPU Direct Storage、KV Cache/Share，不断提升存储系统性能和减少计算。 3. 保障存储系统高可用与数据安全，通过分布式强一致性、同/异步复制提升数据可靠性，设计系统自愈能力应对磁盘/节点异常，增强系统可观测和易运维能力，并通过测试与故障注入得到验证。
候选人主要从事的工作是高性能计算相关的模拟接口IP的研发，包括不限于D2D/Memory/C2C/板卡互联等。候选人需要完成IP的立项、架构、交付、开发、测试等端到端的工作，需要具备如下能力至少一项（第4项为必备项）： 1.IP立项：可以完成IP 的竞争力分析，确定IP 的长期演进技术方向，并完成IP 架构选型、关键技术分析、竞争力构建策略；主导IP 立项。 2.IP架构：完成IP 架构的建模、指标分解、具体电路的方案调研，并跟踪电路的开发，确保指标达成和竞争力的实现。 3.IP 交付：需要熟悉数模混合IP交付的流程，可以配合封装、测试、模型、算法、数字设计、数字验证完成模拟IP 相关交付件的需求梳理、交付件对齐、数模混合验证等工作。 4.IP 开发：需要至少CMU（时钟管理单元）、TX、RX 一个领域有深入的理解，可以选择适配IP 的最有竞争力的方案；并完成组件的设计、指导CL布局布线、 仿真验证等。 5.IP 测试：完成测试需求的收集、评审；测试用例的完备性分析；测试方案的开发和验证；回片的测试的启动和测试问题的攻关。