智能互联平头哥-模拟设计高级/资深专家（高速电芯片-光互联方向）-上海

The candidate will be the major interface to the optical IO analog/mixed signal design team or vendor. As a member of the analog team, you’ll collaborate with our architects and engineers to develop innovative high speed analog transceiver solutions for next-generation optical and wireline communication systems. * We are currently hiring for multiple levels for this role. Your level and compensation will be determined by your experience, education, and location. ● Design analog/mixed-signal blocks with a focus on transceivers and broadband circuits interfacing with silicon photonics elements such as trans-impedance amplifiers (TIA) and Tx Driver ● Contribute to the development of complex SoC integration flows, with a strong focus on high-speed circuit design and advanced node integration. You will work closely with photonics and 3DIC packaging teams to co-develop solutions for leading-edge products ● Support micro-architecture development with chip architects by conducting feasibility studies ● Collaborate with members of our design engineering teams (system, digital, analog, photonics) to define electrical requirements ● Drive block-level floorplan, mask design views, and their reviews ● Run post-layout and mixed-signal top-level simulations to validate integration ● Define production and bench-level test plans ● Validate performances of the circuits in the lab ● Mentor junior design engineers

As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization. You responsibilities include, but not limited to: * Build backend flow on state-of-the-art processing node * Create SPECs for PD sign-off * Work closely with architecture and design team to optimize PPA * Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc. * Design and timing ECOs and sign-offs

1. 负责服务器/交换机产品系统硬件设计，保证产品方案领先性、成本优势和综合竞争力，参与产品端到端交付； 2. 负责原始需求的分析、评估与分解，提前识别风险点，解决开发过程中遇到的问题； 3. 负责推动各领域按照硬件系统方案按期完成开发和测试工作，保证最终硬件系统的交付质量； 4. 负责持续跟踪和分析友商竞品的优劣势，为平头哥产品定义和设计提供参考依据； 5. 跟进业界技术发展趋势，参与平头哥芯片与硬件产品路标的规划；

1. 负责服务器/交换机产品系统硬件设计，保证产品方案领先性、成本优势和综合竞争力，参与产品端到端交付； 2. 负责原始需求的分析、评估与分解，提前识别风险点，解决开发过程中遇到的问题； 3. 负责推动各领域按照硬件系统方案按期完成开发和测试工作，保证最终硬件系统的交付质量； 4. 负责持续跟踪和分析友商竞品的优劣势，为平头哥产品定义和设计提供参考依据； 5. 跟进业界技术发展趋势，参与平头哥芯片与硬件产品路标的规划；