平头哥平头哥-模拟设计高级/资深专家（高速电芯片-光互联方向）-上海
任职要求
● Minimum MSEE with 8+ years or Ph.D. with 5+ years of relevant industry experience with a focus on optical or wireline transceiver design for 20+ Gbps NRZ and PAM applications ● Experience designing Analog-Front-End blocks such as trans-impedance amplifiers (TIA) and Tx Driver ● Experience interfacing with silicon photonic modulators (MZM, MRM) ● Understanding of photonic devices: wave…
工作职责
The candidate will be the major interface to the optical IO analog/mixed signal design team or vendor. As a member of the analog team, you’ll collaborate with our architects and engineers to develop innovative high speed analog transceiver solutions for next-generation optical and wireline communication systems. * We are currently hiring for multiple levels for this role. Your level and compensation will be determined by your experience, education, and location. ● Design analog/mixed-signal blocks with a focus on transceivers and broadband circuits interfacing with silicon photonics elements such as trans-impedance amplifiers (TIA) and Tx Driver ● Contribute to the development of complex SoC integration flows, with a strong focus on high-speed circuit design and advanced node integration. You will work closely with photonics and 3DIC packaging teams to co-develop solutions for leading-edge products ● Support micro-architecture development with chip architects by conducting feasibility studies ● Collaborate with members of our design engineering teams (system, digital, analog, photonics) to define electrical requirements ● Drive block-level floorplan, mask design views, and their reviews ● Run post-layout and mixed-signal top-level simulations to validate integration ● Define production and bench-level test plans ● Validate performances of the circuits in the lab ● Mentor junior design engineers
The candidate will be the major interface to the optical IO analog/mixed signal design team or vendor. As a member of the analog team, you’ll collaborate with our architects and engineers to develop innovative high speed analog transceiver solutions for next-generation optical and wireline communication systems. * We are currently hiring for multiple levels for this role. Your level and compensation will be determined by your experience, education, and location. ● Design analog/mixed-signal blocks with a focus on transceivers and broadband circuits interfacing with silicon photonics elements such as trans-impedance amplifiers (TIA) and Tx Driver ● Contribute to the development of complex SoC integration flows, with a strong focus on high-speed circuit design and advanced node integration. You will work closely with photonics and 3DIC packaging teams to co-develop solutions for leading-edge products ● Support micro-architecture development with chip architects by conducting feasibility studies ● Collaborate with members of our design engineering teams (system, digital, analog, photonics) to define electrical requirements ● Drive block-level floorplan, mask design views, and their reviews ● Run post-layout and mixed-signal top-level simulations to validate integration ● Define production and bench-level test plans ● Validate performances of the circuits in the lab ● Mentor junior design engineers
候选人主要从事的工作是高性能计算相关的模拟接口IP的研发，包括不限于D2D/Memory/C2C/板卡互联等。候选人需要完成IP的立项、架构、交付、开发、测试等端到端的工作，需要具备如下能力至少一项（第4项为必备项）： 1.IP立项：可以完成IP 的竞争力分析，确定IP 的长期演进技术方向，并完成IP 架构选型、关键技术分析、竞争力构建策略；主导IP 立项。 2.IP架构：完成IP 架构的建模、指标分解、具体电路的方案调研，并跟踪电路的开发，确保指标达成和竞争力的实现。 3.IP 交付：需要熟悉数模混合IP交付的流程，可以配合封装、测试、模型、算法、数字设计、数字验证完成模拟IP 相关交付件的需求梳理、交付件对齐、数模混合验证等工作。 4.IP 开发：需要至少CMU（时钟管理单元）、TX、RX 一个领域有深入的理解，可以选择适配IP 的最有竞争力的方案；并完成组件的设计、指导CL布局布线、 仿真验证等。 5.IP 测试：完成测试需求的收集、评审；测试用例的完备性分析；测试方案的开发和验证；回片的测试的启动和测试问题的攻关。
候选人主要从事的工作是高性能计算相关的模拟接口IP的研发，包括不限于D2D/Memory/C2C/板卡互联等。候选人需要完成IP的立项、架构、交付、开发、测试等端到端的工作，需要具备如下能力至少一项（第4项为必备项）： 1.IP立项：可以完成IP 的竞争力分析，确定IP 的长期演进技术方向，并完成IP 架构选型、关键技术分析、竞争力构建策略；主导IP 立项。 2.IP架构：完成IP 架构的建模、指标分解、具体电路的方案调研，并跟踪电路的开发，确保指标达成和竞争力的实现。 3.IP 交付：需要熟悉数模混合IP交付的流程，可以配合封装、测试、模型、算法、数字设计、数字验证完成模拟IP 相关交付件的需求梳理、交付件对齐、数模混合验证等工作。 4.IP 开发：需要至少CMU（时钟管理单元）、TX、RX 一个领域有深入的理解，可以选择适配IP 的最有竞争力的方案；并完成组件的设计、指导CL布局布线、 仿真验证等。 5.IP 测试：完成测试需求的收集、评审；测试用例的完备性分析；测试方案的开发和验证；回片的测试的启动和测试问题的攻关。
候选人主要从事的工作是高性能计算相关的模拟接口IP的研发，包括不限于D2D/Memory/C2C/板卡互联等。候选人需要完成IP的立项、架构、交付、开发、测试等端到端的工作，需要具备如下能力至少一项（第4项为必备项）： 1.IP立项：可以完成IP 的竞争力分析，确定IP 的长期演进技术方向，并完成IP 架构选型、关键技术分析、竞争力构建策略；主导IP 立项。 2.IP架构：完成IP 架构的建模、指标分解、具体电路的方案调研，并跟踪电路的开发，确保指标达成和竞争力的实现。 3.IP 交付：需要熟悉数模混合IP交付的流程，可以配合封装、测试、模型、算法、数字设计、数字验证完成模拟IP 相关交付件的需求梳理、交付件对齐、数模混合验证等工作。 4.IP 开发：需要至少CMU（时钟管理单元）、TX、RX 一个领域有深入的理解，可以选择适配IP 的最有竞争力的方案；并完成组件的设计、指导CL布局布线、 仿真验证等。 5.IP 测试：完成测试需求的收集、评审；测试用例的完备性分析；测试方案的开发和验证；回片的测试的启动和测试问题的攻关。