英伟达Senior System Validation Methodology Engineer

任职要求

NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team. The SSG team is uniquely positioned to have an end-to-end view of the product development cycle - from early arch definition, through bringup, to product release.Our ArchDev arm is a hub for all silicon and system level feature development, cost-benefit analysis, system integration solutions, and system POR alignment. As a member of this team, you will evaluate next gen silicon and define methodology, design, SW/FW, tool requirements needed for HW validation. The work you do will directly benefit the quality of NVIDIA products.
What you'll be doing:
• Lead NVIDIA Product GPU/CPU/SOC IP/system level validation strategy, characterization and tuning methodology, platform/component interoperability, debug capability and tools/scripts, system, SLT, and manufacturing test requirement and lead cross-function teams (ASIC, SW, FW, Board, PHY, SI/PI etc) for development and implementation.
• Lead new feature silicon bring-up, validation, and debug, and coordinate product schedule to release feature with high quality at aggressive schedule.
• Deep dive into technically challenging from Pre-Si and Post-Si bugs and lead debug efforts across cross-functional teams to fix the issue on schedule and envision design optimization and collaborate with designer to implement for next generation.
• Proactively drive and identify opportunities and methods optimization and innovation for test strategies, process and workflow, validation methodology and efficiency based on project learnings and challenging.

What We Need to See:
• MS or BS degree in EE/CE or equivalent experience.
• 8+ years of experience in some of the following areas:
• Deep understanding of GPU/SOC/CPU system level architecture of data center, and HW validation and bringup methodologies cross Pre-si, Post-si, product and Tray/Rack/Cluster level.
• Working experience with system level and interconnect power management optimizations, HSIOs protocol/functional/electrical, Serdes, SI/PI, Clock, PLL, boot, reset, binning, PVT sensitivity, platform integration.
• Working experience on Pre-Si/FPGA and Post-Si validation, debug, rooting cause and fixing against product needs.
• Deep understanding of OS/firmware/driver structures and their interaction with HW.
• Hands on experience with Lab test and measurement equipment.
• Effective collaboration and communication, presentation skills across different functional teams.
With competitive salaries and a generous benefits package,

工作职责

N/A