英伟达Senior ASIC Verification Engineer - Networking Chip Design
任职要求
• Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience. • 3+ years of hands-on experience in ASIC design verification (DV) • Strong team player with excellent communication skills an…
工作职责
• Work within a cross-functional design & verification team focused on end-to-end switch full-chip development • Understand the Switch architecture • Translate switch chip performance targets into comprehensive, structured performance test plans • Understand the IP programming model and develop/maintain DV collaterals accordingly • Develop Fullchip test collaterals/suites, maintain regressions, debug failures and drive coverage sign-off through close collaboration with IP teams • Maintain test suites to facility Emulation and/or Silion platforms checkout as well
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages