英伟达Senior ASIC Verification Engineer - PMU
任职要求
• BS / MS in electrical / computer engineering. • 3+ years working experience, with preference given to those with MS or equivalent experience. • Strong communication skills and proficient oral English since this role require frequent communicat…
工作职责
As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic. It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points. We are seeking a Senior ASIC Engineer who can help architect the next generation PMU for AI datacenter. What you’ll be doing: • Collaborate with the production SW team and power arch team to define the architecture/micro-architecture for various power features. • Learn how PMU's function impacts the system and support the silicon debug. • Implement the micro-architecture to RTL design.
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages
• Work within a cross-functional design & verification team focused on end-to-end switch full-chip development • Understand the Switch architecture • Translate switch chip performance targets into comprehensive, structured performance test plans • Understand the IP programming model and develop/maintain DV collaterals accordingly • Develop Fullchip test collaterals/suites, maintain regressions, debug failures and drive coverage sign-off through close collaboration with IP teams • Maintain test suites to facility Emulation and/or Silion platforms checkout as well
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages
NVIDIA SOC System-ASIC team is hiring a verification engineer. In this role, you will work closely with Arch, design and verification engineers to thoroughly verify some top-level related control units (like: Fuse/Floorsweep, Strap, Reset, Sysctrl) and some silicon measurement related units from unit-level to fullchip-level. Those units are important IPs used in both NVIDIA GPU and Tegra products. What you’ll be doing: • Micro-architecture definition for System-level modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl, etc...) • Unit-level and System-level verification for System-level modules. • Own some NVIDIA internal checks to guarantee the design quality.