英伟达ASIC Design Engineer, Clocks

工作描述

任职要求
• BS or (MS preferred) in EE or equivalent experience. 2+ years of meaningful work experience.
• Your ability to thrive in a dynamically changing environment.
• Validated experience in RTL design (Verilog), verification and logic synthesis. Your strong coding skills in Perl or Python or other industry-standard scripting languages.
• Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus. Good understanding of backend flows and requirements is a plus.
• DFT knowledge is a plus. Experience in implementing on-chip clocking networks is desirable.
• Excellent analytical and problem-solving skills. Fluent English (both written and spoken) and excellent commu…