英伟达ASIC TOP Floorplan Design Engineer
任职要求
• Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work experience. • At least 3+ years of relevant work experience. • A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture. • Experience in Verilog, System Verilog or similar HVL. • Experience with CAD and physical design methodologies (flow and tool develo…
工作职责
• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • You will build tools and improve existing infrastructure to optimize chip area and speed of execution.
• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • You will build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.
• Working with architects, design leads, physical design leads and package leads, you will develop, craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • Build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.
1、负责包括快手视频直播、转码后端的工程化开发与优化； 2、负责流媒体系统的设计与开发； 3、负责音视频的编码、传输、转码、解码等模块的开发； 4、根据需求与总体设计要求，编写技术及接口文档。
1、参与大模型推理/训练优化。通过研发业界领先的AI Compiler 技术，支撑搜推场景在GPU上的训练计算性能优化；支持大模型推理优化技术在异构硬件上的落地； 2、参与各种大模型推理所需的功能性开发任务；相关编译优化功能开发，以图优化、算子融合、GPU高性能算子开发及自动Codegen等技术手段不断推高在不同卡型上的计算性能极限； 3、参与支持日常的大模型推理服务部署，参与内部日常提效工具的研发。