英伟达ASIC Verification Engineer - PMU
任职要求
• BS with 4+ years of experience or MS with 2+ years of working experience. • Self-driving, active thinking and problem solving. • Solid IC background. • Experienced with System Verilog and UVM methodology. Familiar with perl or python script. Familiar with C/C++ coding. • Fluent ora…
工作职责
As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic. It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points. We are seeking a Senior Verification Engineer to join our Power Management Unit (PMU) IP team to help building more powerful PMU engine. What you’ll be doing: • Co-work with the IP architect and designer to define the IP verification methodology and test plan. Finishing the IP verification for all new coming features from project to project. • Maintain and improve the UVM based unit-level TB to be powerful and efficient. Maintain the regression and run various of sing-off verification checklists. • Learn and practice formal verification, and use formal tool to assist simulation to raise the verification quality.
• Study IP/system-level architect to define unitlevel testbench structure. • IP level verification for various features defined for GPU PMU and THERM IP. • Fullchip verification for GPU PMU IP and Tegra THERM IP.
As chip sizes continue to grow, power efficiency has become paramount across all applications - from data centers to automotive and personal computing. Our PMU IP, developed over the past 13 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic. It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points. We are seeking a Senior Verification Engineer to join our Power Management Unit (PMU) IP team to help building more powerful PMU engine. What you’ll be doing: • Co-work with the IP architect and designer to define the IP verification methodology and test plan. Finishing the IP verification for all new coming features from project to project. • Maintain and improve the SV based unit-level TB to be power powerful and efficient. Maintain the regression and run various of sing-off verification checklists. • Learn and practice formal verification, and use formal tool to assist simulation to raise the verification quality.
1、负责包括快手视频直播、转码后端的工程化开发与优化； 2、负责流媒体系统的设计与开发； 3、负责音视频的编码、传输、转码、解码等模块的开发； 4、根据需求与总体设计要求，编写技术及接口文档。
1、参与大模型推理/训练优化。通过研发业界领先的AI Compiler 技术，支撑搜推场景在GPU上的训练计算性能优化；支持大模型推理优化技术在异构硬件上的落地； 2、参与各种大模型推理所需的功能性开发任务；相关编译优化功能开发，以图优化、算子融合、GPU高性能算子开发及自动Codegen等技术手段不断推高在不同卡型上的计算性能极限； 3、参与支持日常的大模型推理服务部署，参与内部日常提效工具的研发。