英伟达ASIC Verification Engineer
任职要求
• BS / MS in electrical / computer engineering and related with 1+ years of ASIC verification experience. • Unit/Sub-system/SOC level verification experience • Strong programming skills in Perl/Python and C/C++, Verilog or SV. • Your proven knowledge/experience with industry standard verification tools for simulation and debug • Confirmed debugging and strong analytical skills. • Familiar with verification methodology, tools and flow. • …
工作职责
The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Verification engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the frontend design team to understand the clocking requirements for the chip. We also understand the physical restrictions being placed on the clocks by the backend teams. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you’ll be doing: • Develop test plans, tests and verification infrastructure for verifying high-speed Clocking logic, including many aspects: function, DFT, circuit, power, physical design constraints, and etc. You would need to comprehend the functional, test and timing modes for clocks RTL and verify the modes before RTL delivery. • You will collaborate with other verification engineers and provide creative solutions to reuse programming sequences across various verification hierarchies. • Build verification environment using SV/UVM methodology Build reusable bus functional models, monitors, checkers and scoreboards • Drive coverage driven verification closure • Work with architects, designers and post-silicon teams. • Methodology development for above tasks.
As chip sizes continue to grow, power efficiency has become paramount across all applications - from data centers to automotive and personal computing. Our PMU IP, developed over the past 13 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic. It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points. We are seeking a Senior Verification Engineer to join our Power Management Unit (PMU) IP team to help building more powerful PMU engine. What you’ll be doing: • Co-work with the IP architect and designer to define the IP verification methodology and test plan. Finishing the IP verification for all new coming features from project to project. • Maintain and improve the SV based unit-level TB to be power powerful and efficient. Maintain the regression and run various of sing-off verification checklists. • Learn and practice formal verification, and use formal tool to assist simulation to raise the verification quality.
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages
• Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages
NVIDIA SOC System-ASIC team is hiring a verification engineer. In this role, you will work closely with Arch, design and verification engineers to thoroughly verify some top-level related control units (like: Fuse/Floorsweep, Strap, Reset, Sysctrl) and some silicon measurement related units from unit-level to fullchip-level. Those units are important IPs used in both NVIDIA GPU and Tegra products. What you’ll be doing: • Micro-architecture definition for System-level modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl, etc...) • Unit-level and System-level verification for System-level modules. • Own some NVIDIA internal checks to guarantee the design quality.