英伟达Senior Custom Silicon Design Engineer
任职要求
• B.S. or M.S. in Computer Engineering or Electrical Engineering (or equivalent experience) • 9+ years of relevant work experience in RTL development focused on CPU, GPU, and high-performance architectures. • Proficiency in industry-standard RTL development and synthesis tools. • Experience developing high-speed digital blocks. • Experience debugging complex microarchitectural structures • Strong interpersonal, communication, and teamwork skills. • A drive to continuously learn and expand architectural breadth and depth. • …
工作职责
• Working with customers, partners, and IP vendors to understand SOC/IP solutions best suited for the target use cases and work with them to select and integrate appropriate IP/SOC solutions. • Work with Architects, Chip Leads, and Customers on SOC/IP design, development, timing closure, power analysis, methodology alignment, and program execution to ensure pre-silicon and post-silicon targets are met. • Integrating, evolving, and optimizing IP blocks across a range of products and use cases for NVIDIA SoCs in AI, driving, 6G, cloud, gaming, and other applications. • Working with teams throughout the company (Architects, RTL, PD, Circuit, SI, Thermal, SW, Platform, Operations, Marketing, etc...) on implementing cross-team solutions to achieve project targets. • Drive cross-team methodologies for external soft IP and PHY integration, Nvidia IP release to partner, RTL development and microarchitecture.
• Responsible for ASIC design verification for various IPs at IP and SOC levels • Responsible for reference model development and integration • Participate in IP/SOC architecture, micro-architecture reviews, interface with Architecture, SW/FW, Design, and Modeling to work out comprehensive first-time right verification plans • Contribute to the innovative verification methodology development, functional and code coverage closure. • Work on the complex TB creation, direct/random tests and drive the function and coverage to closure. • Contribute to the development of silicon and platform verification strategy and methodology • Triage the fail on SOC level with SOCV/EMU/SW team • Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection, and IP licensing
As chip sizes continue to grow, power efficiency has become paramount across all applications - from data centers to automotive and personal computing. Our PMU IP, developed over the past 13 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic. It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points. We are seeking a Senior ASIC Engineer who can help architect the next generation PMU for AI datacenter. What you’ll be doing: • Collaborate with the production SW team and power arch team to define the architecture/micro-architecture for various power features. • Learn how PMU's function impacts the system and support the silicon debug. • Implement the micro-architecture to RTL design.
THE ROLE: AMD’s Strategic Silicon Solutions group is responsible for custom silicon for advanced gaming platforms such as XBOX, PlayStation, and Steam Deck. As a Principal Post-Silicon Power and Performance Engineer you will play a critical role in ensuring our custom silicon products meet power and performance targets and are optimized for customer use cases. You will partner with architecture, software, manufacturing, and other teams to develop a deep understanding of power and performance requirements and work with a multi-site team of engineers to develop and execute studies to validate products meet specifications. The role requires extensive data analysis and communication of results with customers and senior leaders. THE PERSON: We are looking for a technical expert with extensive experience in x86, ARM, or GPU hardware or firmware development with a passion for power validation and optimization spanning low-power mobile to console-level devices. Our ideal candidate thrives in a global, cross-functional environment – partnering with engineering teams across multiple time countries and time zones to solve complex technical challenges and deliver exceptional results. KEY RESPONSIBILITIES: Build deep expertise in existing and emerging power and performance features. Apply expertise to develop strategies for achieving power or performance targets, drive overall validation and tuning of power or performance features and partner with manufacturing and customer engineering to ensure production readiness. Collaborate with key internal and external stakeholders.
• Design, develop, and deploy robust AI/ML systems with high-quality, scalable, and maintainable code • Translate complex, ambiguous requirements into clear technical plans and lead project execution across engineering efforts • Build scalable infrastructure and platforms to support cutting-edge machine learning workflows, including agentic systems that can plan, reason, and act autonomously • Research and apply state-of-the-art ML techniques—including LLMs, custom model training, and RAG/agent-based architectures—to real-world hardware challenges • Stay current with the fast-evolving AI/ML landscape, continuously improving our tools, systems, and methods to maintain a technical edge • Provide technical mentorship, foster a culture of excellence and inclusion, and help grow team capabilities • Lead design discussions, author technical documentation, and provide thoughtful, actionable feedback to peers • Represent the team in executive reviews, product demos, retrospectives, and cross-functional forums