英伟达Senior Custom Silicon Design Engineer
任职要求
• B.S. or M.S. in Computer Engineering or Electrical Engineering (or equivalent experience) • 9+ years of relevant work experience in RTL development focused on CPU, GPU, and high-performance architectures. • Proficiency in industry-standard RTL development and synthesis tools. • Experience developing high-speed digital blocks. • Experience debugging complex microarchitectural structures • Strong interpersonal, communication, and teamwork skills. • A drive to continuously learn and expand architectural breadth and depth. • …
工作职责
• Working with customers, partners, and IP vendors to understand SOC/IP solutions best suited for the target use cases and work with them to select and integrate appropriate IP/SOC solutions. • Work with Architects, Chip Leads, and Customers on SOC/IP design, development, timing closure, power analysis, methodology alignment, and program execution to ensure pre-silicon and post-silicon targets are met. • Integrating, evolving, and optimizing IP blocks across a range of products and use cases for NVIDIA SoCs in AI, driving, 6G, cloud, gaming, and other applications. • Working with teams throughout the company (Architects, RTL, PD, Circuit, SI, Thermal, SW, Platform, Operations, Marketing, etc...) on implementing cross-team solutions to achieve project targets. • Drive cross-team methodologies for external soft IP and PHY integration, Nvidia IP release to partner, RTL development and microarchitecture.
• Responsible for ASIC design verification for various IPs at IP and SOC levels • Responsible for reference model development and integration • Participate in IP/SOC architecture, micro-architecture reviews, interface with Architecture, SW/FW, Design, and Modeling to work out comprehensive first-time right verification plans • Contribute to the innovative verification methodology development, functional and code coverage closure. • Work on the complex TB creation, direct/random tests and drive the function and coverage to closure. • Contribute to the development of silicon and platform verification strategy and methodology • Triage the fail on SOC level with SOCV/EMU/SW team • Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection, and IP licensing
* Large-Scale Training Pipelines: Design and implement distributed training pipelines for LLMs using tools such as Fully Sharded Data Parallel (FSDP) and DeepSpeed, ensuring scalability and efficiency * LLM Customization & Fine-Tuning: Adapt LLMs for new languages, domains, and vision applications through continued pre-training, fine-tuning, and Reinforcement Learning with Human Feedback (RLHF) * Model Optimization on AWS Silicon: Optimize AI models for deployment on AWS Inferentia and Trainium, leveraging the AWS Neuron SDK and developing custom kernels for enhanced performance * Customer Collaboration: Interact with enterprise customers and foundational model providers to understand their business and technical challenges, co-developing tailored generative AI solutions
As chip sizes continue to grow, power efficiency has become paramount across all applications - from data centers to automotive and personal computing. Our PMU IP, developed over the past 13 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic. It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points. We are seeking a Senior ASIC Engineer who can help architect the next generation PMU for AI datacenter. What you’ll be doing: • Collaborate with the production SW team and power arch team to define the architecture/micro-architecture for various power features. • Learn how PMU's function impacts the system and support the silicon debug. • Implement the micro-architecture to RTL design.
As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic. It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points. We are seeking a Senior ASIC Engineer who can help architect the next generation PMU for AI datacenter. What you’ll be doing: • Collaborate with the production SW team and power arch team to define the architecture/micro-architecture for various power features. • Learn how PMU's function impacts the system and support the silicon debug. • Implement the micro-architecture to RTL design.