英伟达Physical Design Intern, VLSI - 2026

• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • You will build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.

• Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan • Synthesis, RTL/netlist quality check, formal verification, function eco creation • Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async etc. • Work in conjunction with PR engineers for chip implementation to achieve full chip timing closue • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout), flow automation development for above areas • Methodology in any of above areas.

An exciting internship opportunity to make an immediate contribution to AMD's next generation of technology innovations awaits you! We have a multifaceted, high-energy work environment filled with a diverse group of employees, and we provide outstanding opportunities for developing your career. During your internship, our programs provide the opportunity to collaborate with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more. Being part of AMD means receiving hands-on experience that will give you a competitive edge. Together We Advance your career! JOB DETAILS: THE ROLE: Work with talented colleague cross different sites in different countries, to achieve a goal of tapeout on time after all needed sign-off checks. You will be in key position of handling quality of gds delivered to foundry and AMD will provide you a great platform of learning most advanced silicon technologies and exhibiting your excellent skill and personalities. THE PERSON: Given that you will work with teams abroad, English communication skill is a must and team work is also important for our daily work. As a plus, dedicated and innovative sprit is welcomed. KEY RESPONSIBILITIES: Focus on physical verification like DRC, LVS, Antenna, ESD, Latch-up, PERC checks in projects to ensure allocated work can be done within target timeline, to finally make sure tapeout on time. Have chance to learn all PhyV related knowledge and thus have a clear overview of how a large SOC works and how it pass all required verifications till a successful tapeout. Will have chance to exhibit your innovative ideas of enhancing current work flow or creating new tools/flow to automate daily work to increase efficiency.

The NVIDIA SOC group is looking for ASIC design/verification/infrastructures and methodologies interns. In this position, you will take part in all stages to design modern complex GPU/Tegra chips with state-of-art feature and flows, you will work directly with different global teams, as Arch/SW, ASIC Design/Verification, SOCD/Clocks/SysASIC, DFT and Physical Design teams. Additionally, you will be involved in defining and creating infrastructures and methodologies that create more efficient and flexible SOCs in future. What you’ll be doing: • Participate in chip top integration and assembly • Engage in design/verification work of system-level units • Optimize composing/verification flow, processes, and methodologies • Develop new tools and flows to improve efficiency and quality