英伟达Physical Design Engineer
任职要求
• BS in Engineering or Science or equivalent experience. • Power user of EDA tools from Synopsys (ICC2/FC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus). • Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes. • 2+ years of experie…
工作职责
We are now looking for a Physical Design Engineer. VLSI Physical Design Team at NVIDIA Shanghai has been built up since 2005. The team has made contribution to various successful products launched by NVIDIA Corporation over 15 years. We utilize latest process technology, advanced EDA tools, and sophisticated design methodology. We always work on the most challenging designs, and push for performance limit. What you’ll be doing: • A role in physical design for NVIDIA GPU and Mobile chips. • Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. • Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.
• Chip integration and netlist generation • Synthesis, RTL/netlist quality check, Formal Verification • Constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure • Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation and method development • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Methodology and flow automation development for above areas.
• Chip integration and netlist generation • Synthesis • RTL/netlist quality check, Formal Verification, constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level; Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation; Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Flow automation development for above areas; Methodology in any of above areas.
THE ROLE: We are looking for an adaptive, self-motivative physical design engineer to join our team. As a key contributor, you will be part of a engineering team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Phyiscal Design Engineering team, as part of SoC team, furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
THE ROLE: AMD CAD team is part of Design Methodology team and be responsible to deliver differentiated ASIC implementation flows (from RTL to GDSII) for all AMD products. You'll be working with the global CAD team on physical design implementation flows (from netlist to GDSII) and focus on PPA push related areas.