英伟达Mask Layout Design Engineer - New College Graduate 2026
任职要求
NVIDIA has continuously reinvented itself over decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can pursue, and for that matter to the world. This is our life’s work, to amplify human creativity and intelligence.Are you interested in designing circuits for the next generation of AI chips? Join a team of dedicated engineers developing custom digital IPs. You will have the chance to learn novel low-power and high-performance circuits and you will showcase your layout design talent at the latest and smallest process node at the earliest time. We are now looking for Mask Layout Designers, NCG. If someone who desires to join a dynamic group of diverse individuals responsible for dealing with high-speed digital IP layouts, do not miss this opportunity. What You'll Be Doing: • Physical layout of STD cells, ROMs, and compiled RAMs on each most advanced foundry processes with earlier and unstable design environments. • Work closely with NVIDIA talents to speed up layout production including customized DRC/LVS, and plenty of specific verification development, testing, and debug. What We Need To See: • Pursuing MS or PH.D. in MS Microelectronics, Semiconductor Physics or rel…
工作职责
N/A
1. Frame 布局设计及 marK设计； 2. Kerf rule building； 3. Mask tape-out 流程自动化开发； 4. 提供产品框架图设计的解决方案；
The candidate will be the major interface to the optical IO analog/mixed signal design team or vendor. As a member of the analog team, you’ll collaborate with our architects and engineers to develop innovative high speed analog transceiver solutions for next-generation optical and wireline communication systems. * We are currently hiring for multiple levels for this role. Your level and compensation will be determined by your experience, education, and location. ● Design analog/mixed-signal blocks with a focus on transceivers and broadband circuits interfacing with silicon photonics elements such as trans-impedance amplifiers (TIA) and Tx Driver ● Contribute to the development of complex SoC integration flows, with a strong focus on high-speed circuit design and advanced node integration. You will work closely with photonics and 3DIC packaging teams to co-develop solutions for leading-edge products ● Support micro-architecture development with chip architects by conducting feasibility studies ● Collaborate with members of our design engineering teams (system, digital, analog, photonics) to define electrical requirements ● Drive block-level floorplan, mask design views, and their reviews ● Run post-layout and mixed-signal top-level simulations to validate integration ● Define production and bench-level test plans ● Validate performances of the circuits in the lab ● Mentor junior design engineers
1. Lead the RET solution path findings in advanced nodes of DRAM processes. 2. Maintain and develop new recipes to deliver robust post OPC solutions to the apeout team. 3. Engage with layout/device/integration teams on the DFM/DTCO flow delivery. 4. Trouble shooting with inline defects and provide possible RET/OPC supports. 5. Optimize the RET/OPC flow to improve the TAT and efficiency.
1. 负责各类项目的tapeout工作, 对半导体物理，器件原理，工艺制造流程，存储电路，layout设计，mask制作，封装，脚本语言都有一定的了解。 2. 负责frame GDR定义，需要和PIE/litho紧密沟通，了解不同工艺对frame设计规则的定义，并实现DRC deck对frame进行有限的验证。 3. tapeout数据处理，需要对客户chip级layout进行dum和LO的数据处理以及和各户进行有效的及时沟通和反馈直到数据准确无误的tapeout。