长江存储Tapeout整合工程师(J13570)
任职要求
1. 熟悉半导体物理，器件原理，工艺制造流程。 2. 对存储芯片基本原理和电路，layout设计，mask制作，封装都有一定的了解。 3. 熟悉两种脚本语言最佳，如：Phthon/perl/Shell。
工作职责
1. 负责各类项目的tapeout工作, 对半导体物理，器件原理，工艺制造流程，存储电路，layout设计，mask制作，封装，脚本语言都有一定的了解。 2. 负责frame GDR定义，需要和PIE/litho紧密沟通，了解不同工艺对frame设计规则的定义，并实现DRC deck对frame进行有限的验证。 3. tapeout数据处理，需要对客户chip级layout进行dum和LO的数据处理以及和各户进行有效的及时沟通和反馈直到数据准确无误的tapeout。
1.从事 DRAM工艺制程研发工作。主要以实现关键技术节点器件电学性能为目的，对各种先进单点工艺制程进行极高要求的整合, 使之成为支撑各种DRAM产品的工艺技术平台。其中大部分的工作内容涉array架构设计以及integration实现方案, 电学表征部门以及具体的制程研发工程师共同进行技术创新, 以达成高水平的电学性能和可靠性能的pathfinding技术； 2.能独立建立至少一个loop的process，实现MTS on target，把控 process development整体timeline，并注重handle lot的细节，早期预防任何contamination 案件的发生，精确并及时分析experiment lot的inline以及电性数据； 3.具备对新型DRAM做系统性调研的能力，其中包括新型阵列存储架构，器件结构，晶体管/电容器材料，以及关键工艺和工艺集成的信息调研； 4.新架构mask tapeout，对TEG设计，外围电路设计，工艺及器件仿真有一定程度的了解，能够与相关领域的专家对接并开展工作，了解Design rule，并具有独立tapeout mask的能力。
1.Be responsible for the design and development of the device architecture of 3D NAND Flash, and deeply participate in the whole process from concept design to mass production. Utilize professional knowledge to carry out innovation at the architecture level, optimize the structure of memory cells, and improve storage density, performance and reliability. 2.Collaborate with the circuit design team to complete the efficient transformation from device physical characteristics to circuit logic, ensuring the compatibility and performance of the overall system. And increase the read and write speed and reduce power consumption. 3.Lead the research and application of new technologies, explore cutting-edge fields such as new materials and manufacturing processes, and provide technical support for the performance breakthrough of 3D NAND Flash. Through the research on industry trends, promote technological innovation and enhance product competitiveness. 4.Conduct in-depth analysis of the problems in the R&D process by using the knowledge of device physics and semiconductor processes, and put forward effective solutions. Use data analysis and modeling techniques to optimize device performance and ensure that products meet high-quality standards. 5.Lead/Participate in test chip tapeout for new memory technology development and product chip tapeout for production introduction 6.Interact with process module, material, simulation, device characterization and reliability group to optimize process flow, improve memory cell device performance and develop innovative solution to meet product requirement and qualification criteria 7. Drive cross-functional team including process module, device, product engineering, design, YE, YAE, TO, and Test to address process/technology gap and yield/margin issues
1.进行基于DRAM制程的HKMG工艺平台整合研发工作。与Design和Device Team根据高性能DRAM的产品需求,提炼出对器件的关键尺寸要求,电性要求和可靠性要求;领导Device以及Module等研发部门通过技术创新,新机台引进,开发出适用于DRAM工艺平台high thermal budget特点的件； 2.开发HKMG工艺的PDK(Design Rule, EDR, Device Model...)应用到NN,N+1,N+2代DRAM平台,同时整合优化制程与前后道工艺实现兼容,最终实现高速低漏电的电学性能能,高可靠性的终端产品要求； 3.新产品导入以及良率提升。从与design合作开始参与新产品设计评估;与tapeout team合作设计testkey,tape out光罩;与制程和生产部门合作pilot run;不断进行工艺整合的优化升级,提升电学性能,可靠性能以及良率。
1.进行先进CMOS工艺平台研发工作。 2.开发CMOS工艺的PDK(Design Rule, EDR, Device Model...),同时整合优化制程与前后道工艺实现兼容,最终实现高速低漏电的电学性能能,高可靠性的终端产品要求。 3.新产品导入以及良率提升。从与design合作开始参与新产品设计评估;与tapeout team合作设计testkey,tape out光罩;与制程和生产部门合作pilot run;不断进行工艺整合的优化升级,提升电学性能,可靠性能以及良率