AMDSOC Physical Design Engineer
任职要求
You have a passion for cutting-edge semiconductor technology, digital design, and physical design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: MSEE with 2+ years or Bachelor with 5+ years of industrial experience in ASIC design Familiar with Back-End (physica…
工作职责
THE ROLE: We are looking for an adaptive, self-motivative physical design engineer to join our team. As a key contributor, you will be part of a engineering team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Phyiscal Design Engineering team, as part of SoC team, furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
THE ROLE: The focus of this role is to do physical implementation on USB PHY tile APR. Combine timing closure with deep dive on constraint clean up.
THE ROLE: The focus of this role is to do physical implementation on USB PHY tile APR. Combine timing closure with deep dive on constraint clean up.
THE ROLE: A Front-End Silicon Design and Integration (FEINT) Engineering role in our GFX Memory Controller IP (GMCIP) team. GFX Memory controller provides high performance functions to System on Chip (SoC) products across all AMD business units such as GPU AI accelerators, graphics and gaming. Our FEINT engineers will perform RTL synthesis and PPA analysis in order to improve the QoR of RTL designs. They will also create, adopt and automate RTL static design rule checks, perform ECO and LEC checks. THE PERSON: A talented FEINT engineer with strong records of technical ownership and execution to drive synthesis, PPA analysis, Power redux, ECO, and static verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. KEY RESPONSIBILITIES: Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result) Develop power redux strategy such as hierarchical CG (clock gating) at multiple levels including RTL and gate level, to ensure power target attainment Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies Develop, adopt and automate RTL static design rule checks in collaboration with Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team Develop and adopt FEINT design and verification infrastructure, methodology and tools
THE ROLE: AMD seeks a passionate, collaborative leader with strong technical skills in the area of Design-for-Test (DFT) and the initiative to motivate an expert design team. The successful candidate will lead a high performance central DFT design team to develop advanced DFT features, tools and flows for high performance, adaptive compute products for AI data center, emdedded, gaming and PC markets.