AMDSOC Physical Design Engineer
任职要求
You have a passion for cutting-edge semiconductor technology, digital design, and physical design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: MSEE with 2+ years or Bachelor with 5+ years of industrial experience in ASIC design Familiar with Back-End (physical design) EDA tools Hands on experience in large scale ASIC chip physical design Knowledgeable in all aspects of deep submicron ASIC design flow Successfully gone through several complete product development cycles Demonstrate strong problem-solving and work well with cross-functional teams Good listening, writing and speaking English Good communication skills, strong interpersonal skills and flexibility Dedicated, hardworking and good team player Familiar with Unix/Linux environment and good at scripts
工作职责
THE ROLE: We are looking for an adaptive, self-motivative physical design engineer to join our team. As a key contributor, you will be part of a engineering team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Phyiscal Design Engineering team, as part of SoC team, furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
THE ROLE: A Front-End Silicon Design and Integration (FEINT) Engineering role in our GFX Memory Controller IP (GMCIP) team. GFX Memory controller provides high performance functions to System on Chip (SoC) products across all AMD business units such as GPU AI accelerators, graphics and gaming. Our FEINT engineers will perform RTL synthesis and PPA analysis in order to improve the QoR of RTL designs. They will also create, adopt and automate RTL static design rule checks, perform ECO and LEC checks. THE PERSON: A talented FEINT engineer with strong records of technical ownership and execution to drive synthesis, PPA analysis, Power redux, ECO, and static verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. KEY RESPONSIBILITIES: Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result) Develop power redux strategy such as hierarchical CG (clock gating) at multiple levels including RTL and gate level, to ensure power target attainment Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies Develop, adopt and automate RTL static design rule checks in collaboration with Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team Develop and adopt FEINT design and verification infrastructure, methodology and tools
The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Verification engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the frontend design team to understand the clocking requirements for the chip. We also understand the physical restrictions being placed on the clocks by the backend teams. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you’ll be doing: • Develop test plans, tests and verification infrastructure for verifying high-speed Clocking logic, including many aspects: function, DFT, circuit, power, physical design constraints, and etc. You would need to comprehend the functional, test and timing modes for clocks RTL and verify the modes before RTL delivery. • You will collaborate with other verification engineers and provide creative solutions to reuse programming sequences across various verification hierarchies. • Build verification environment using SV/UVM methodology Build reusable bus functional models, monitors, checkers and scoreboards • Drive coverage driven verification closure • Work with architects, designers and post-silicon teams. • Methodology development for above tasks.
• Working closely with the development teams, early in the product development lifecycle, to define functional and performance tests. Be the key person concerning calibration, test stations and diagnostics to ensure the product performs at the highest level • Responsible for leading all the ongoing factory tests being conducted in the Mobile Group, for new product introduction from prototype to mass production. • Responsible for the development of test procedures, test plans and test reports. Developing/executing project plans. • Specifying/implementing test process control and data collection, detailing all the ongoing tests. • Be the key liaison between our organization and our Contract Manufacturers • Interact with internal groups at Apple to ensure that tests are being performed adequately and on time. • Responsible for communicating to executives, upper management and technical staff on the progress of our product development and calibration/ test maturity. • This position requires ability to deal with dynamic and fast-paced environment requiring decision-making with ambiguous information.
- Working closely with the development teams, early in the product development lifecycle, to define functional and performance tests. Be the key person concerning calibration, test stations and diagnostics to ensure the product performs at the highest level - Responsible for leading all the ongoing factory tests being conducted in the Mobile Group, for new product introduction from prototype to mass production. - Responsible for the development of test procedures, test plans and test reports. Developing/executing project plans. - Specifying/implementing test process control and data collection, detailing all the ongoing tests. - Be the key liaison between our organization and our Contract Manufacturers - Interact with internal groups at Apple to ensure that tests are being performed adequately and on time. - Responsible for communicating to executives, upper management and technical staff on the progress of our product development and calibration/ test maturity. - This position requires ability to deal with dynamic and fast-paced environment requiring decision-making with ambiguous information.