AMDPhysical Design Engineer

We are now looking for a Physical Design Engineer. VLSI Physical Design Team at NVIDIA Shanghai has been built up since 2005. The team has made contribution to various successful products launched by NVIDIA Corporation over 15 years. We utilize latest process technology, advanced EDA tools, and sophisticated design methodology. We always work on the most challenging designs, and push for performance limit. What you’ll be doing: • A role in physical design for NVIDIA GPU and Mobile chips. • Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. • Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.

We are now looking for a Physical Design Engineer. VLSI Physical Design Team at NVIDIA Shanghai has been built up since 2005. The team has made contribution to various successful products launched by NVIDIA Corporation over 15 years. We utilize latest process technology, advanced EDA tools, and sophisticated design methodology. We always work on the most challenging designs, and push for performance limit. What you’ll be doing: • A role in physical design for NVIDIA GPU and Mobile chips. • Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. • Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.

THE ROLE: The focus of this role is to do physical implementation on USB PHY tile APR. Combine timing closure with deep dive on constraint clean up.

• Chip integration and netlist generation • Synthesis, RTL/netlist quality check, Formal Verification • Constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure • Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation and method development • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Methodology and flow automation development for above areas.