AMDIP Design Verification Engineer
任职要求
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Role is IP DV Engineer Collaborate with architects and hardware engineers to understand the new features to be verified …
工作职责
THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s AXI HUB IP, resulting in no bugs in the final design.
• Responsible for ASIC design verification for various IPs at IP and SOC levels • Responsible for reference model development and integration • Participate in IP/SOC architecture, micro-architecture reviews, interface with Architecture, SW/FW, Design, and Modeling to work out comprehensive first-time right verification plans • Contribute to the innovative verification methodology development, functional and code coverage closure. • Work on the complex TB creation, direct/random tests and drive the function and coverage to closure. • Contribute to the development of silicon and platform verification strategy and methodology • Triage the fail on SOC level with SOCV/EMU/SW team • Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection, and IP licensing
• Study IP/system-level architect to define unitlevel testbench structure. • IP level verification for various features defined for GPU PMU and THERM IP. • Fullchip verification for GPU PMU IP and Tegra THERM IP.
• Participate in the research of verification methodology to improve automation and productivity to produce NVIDIA's new high-quality products. • Read the IAS and design specs to understand the design requirements and build a corresponding test plan. Review the testplan with arch/design engineers. • You responses to build a block/IP testbench based on UVM methodology. • The responsibilities include building a test run and a regression flow. Triage failures in regression and help the designer root cause the bug. • Work includes building various metrics (passing rate, functional coverage, etc) and monitoring its health. • Take SOC verification on full chip test environment for IPs • Analyse functional/code coverage results and identify the coverage holes. Work with the design engineer to improve the coverage score. • Deploy the advanced verification methodology and infrastructure of the SOC/IP
• You will participate in the research of verification methodology to improve automation and productivity to produce NVIDIA's new high-quality products. • Read IAS and design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers. • You responses to build block/IP testbench based on UVM methodology. • The responsibilities include building test run and regression flow. Triage failures in regression and help designer root cause the bug. • Work includes Build various metrics (passing rate, functional coverage, etc) and monitor its health. • Take SOC verification on fullchip test environment for IPs • Analyse functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score. • Deploy the advanced verification methodology and infrastructure of the SOC/IP