长江存储Digital Design Engineer(J14541)
任职要求
- BS or MS in electric and electronic engineering；
- Relevant experience in memory or storage design a plus;
- Skills of Verilog RTL coding, simulation debug and base or metal layer ECO;
- Hands on experi…工作职责
- Write Micro-Architecture Definition/Writing Design Implementation Spec based on memory or storage feature requirements； - Write RTL coding for block or top level； - Do IP level synthesis / timing analysis / formality check / CDC check /Code coverage check； - Assist on Verification Engineer to complete module and top level simulation and verification; - Debug RTL/Gate Level waveform at module or top level; - Do Silicon debugging of the related module functionalities and provide ECO solution accordingly；
1. 模块级架构设计：针对前沿工艺和规格，主导高速存储接口PHY IP的模块级规格制定与架构实现，确保设计符合性能与功耗目标； 2. Chiplet接口开发：推动Chiplet接口模块的规格制定与架构实现，拉通跨模块协同，确保接口兼容性与数据完整性； 3. 高速内存接口实现：参与高速内存接口的高层次产品规范与微架构定义，主导RTL编码、LINT检查及健全性测试，确保代码质量与功能正确； 4. 硬件验证与调试：支持硬件FPGA设计及bring-up，协同验证团队进行实验室调试，推动问题闭环； 5. 系统性能优化：与软件团队和/或客户合作，识别并解决系统级问题，主导调试与系统性能调优，达成设计指标。
1. 全数字锁相环架构设计：主导全数字锁相环的架构规划，完成包括数字控制振荡器、时间数字转换器及数字环路滤波器的RTL实现，优化分数分频频率合成方案； 2. 数字校准与补偿算法实现：设计并实现DCO粗/细调谐校准、TDC线性校正、温度/电压补偿等数字校准环路，以及锁检测、周期滑移检测和扩频时钟控制器； 3. 混合信号验证与性能分析：搭建混合信号验证环境，通过时域仿真、相位噪声分析与抖动直方图验证，确保ADPLL性能满足系统指标； 4. 数字滤波器与调制器控制逻辑开发：设计并优化高分辨率Sigma-Delta ADC的数字抽取滤波器，以及DAC失配校正、失调消除、增益/相位误差修调等数字校准引擎； 5. RTL交付与物理实现：交付满足可综合性、可测试性及DFT要求的量产级RTL代码，主导逻辑综合、时序收敛与功耗优化，协同模拟团队定义数字/模拟接口及时钟方案。
Responsibility: - To build power distribution architecture with embedded digital solution to enhance: o Operation efficiency o Predict maintenance o Grids reliability etc. - Be able to create the application based on the architecture with selected sensors, data collector, control module, gateway, and SCADA. - Validate (test) to secure the quality of the application from a system view: o Coding quality o Application reliability, including functional test, limit test, boundary test, compatibility etc.) o Basic EMC knowledge to ensure the robustness of communication on site - Design the application with modular design concept, to ensure the flexibility of reuse
• Co-work with the architect to define module architecture/micro-architecture. • Building for NVIDIA next next-generation IPs • Involved in the entire ASIC flow.